k3_udma_glue_disable_tx_chn(common->tx_chns[i].tx_chn);
        }
 
+       reinit_completion(&common->tdown_complete);
        k3_udma_glue_tdown_rx_chn(common->rx_chns.rx_chn, true);
+
+       if (common->pdata.quirks & AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ) {
+               i = wait_for_completion_timeout(&common->tdown_complete, msecs_to_jiffies(1000));
+               if (!i)
+                       dev_err(common->dev, "rx teardown timeout\n");
+       }
+
        napi_disable(&common->napi_rx);
 
        for (i = 0; i < AM65_CPSW_MAX_RX_FLOWS; i++)
 
        if (cppi5_desc_is_tdcm(desc_dma)) {
                dev_dbg(dev, "%s RX tdown flow: %u\n", __func__, flow_idx);
+               if (common->pdata.quirks & AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ)
+                       complete(&common->tdown_complete);
                return 0;
        }
 
 };
 
 static const struct am65_cpsw_pdata am64x_cpswxg_pdata = {
-       .quirks = 0,
+       .quirks = AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ,
        .ale_dev_id = "am64-cpswxg",
        .fdqring_mode = K3_RINGACC_RING_MODE_RING,
 };