Recent changes
======================================================================
+* Big Patch by Ian Scott <ISCOTT@altera.com>
+ - add creation of armboot.hex
+ - add Support for the Altera EPXA1 Development Board Excalibur
+ - add smc_set_mac_addr() capability to SMC91111 driver
+ - call epxa1db_set_mac_addr() from board.c (should be revised into
+ something more generic)
+
+* Fix endianess when loading uncompressed images (Ian Scott
+ <iscott@altera.com>)
+
+* Add support for the Altera XA1 Excalibur Development board
+ (Ian Scott <iscott@altera.com>)
+
* Fix tmp string in cmd_net.c (Kyle Harris <kharris@nexus-tech.net>)
* Added FAQ
N: David Müller
E: d.mueller@elsoft.ch
D: Support for Samsung ARM920T SMDK2410 eval board
+
+N: Iain Scott
+E: iscott@altera.com
+D: Initial support for the Altera XA1 development board
smdk2410 ARM920T
+Iain Scott <i.scott@altera.com>
+
+ epxa1db ARM922T (EPXA1)
+
#########################################################################
# End of MAINTAINERS list #
#########################################################################
## ARM9 Systems
#########################################################################
-LIST_ARM9="samsung smdk2410"
+LIST_ARM9="samsung smdk2410 epxa1db"
LIST_all="${LIST_SA} ${LIST_ARM7} ${LIST_ARM9}"
-#
# (C) Copyright 2000, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
#########################################################################
-all: armboot.srec armboot.bin
+all: armboot.srec armboot.hex armboot.bin
install: all
cp armboot.bin /tftpboot/armboot.bin
armboot.srec: armboot
$(OBJCOPY) ${OBJCFLAGS} -O srec $< $@
+armboot.hex: armboot
+ $(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@
+
armboot.bin: armboot
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
armboot: depend subdirs $(OBJS) $(LDSCRIPT)
- $(LD) $(LDFLAGS) $(OBJS) -Map armboot.map -o armboot $(LIBGCC)
+ $(LD) $(LDFLAGS) $(LDFLAGS_EXTRA) $(OBJS) $(LIBGCC) $(EXTERN_LIB) -Map armboot.map -o armboot
subdirs:
@for dir in $(SUBDIRS) ; do $(MAKE) -C $$dir || exit 1 ; done
#########################################################################
unconfig:
- rm -f include/config.h include/config.mk
+ rm -f include/config.h include/config.mk include/epxa/excalibur.h
+
#########################################################################
## ARMv4 Systems
echo "CPU = arm920t" >>config.mk ; \
echo "#include <configs/config_$(@:_config=).h>" >config.h
+#########################################################################
+## ARM922T Systems
+#########################################################################
+
+epxa1db_config : unconfig
+ @echo "Configuring for $(@:_config=) Board..." ; \
+ cd include ; \
+ echo "ARCH = arm" > config.mk ; \
+ echo "BOARD = epxa1db" >>config.mk ; \
+ echo "CPU = epxa" >>config.mk ; \
+ echo "#include <configs/config_$(@:_config=).h>" >config.h
+ @ln -sf ../../board/$(@:_config=)/quartus/excalibur.h include/epxa/excalibur.h
+ @echo "** See the README in board/epxa1db for build instructions **"
+
#########################################################################
clean:
- find . -type f \
+ find . -path './tools/quartus' -prune -o -type f \
\( -name 'core' -o -name '*.bak' -o -name '*~' \
-o -name '*.o' -o -name '*.a' -o -name '.depend' \) -print \
| xargs rm -f
clobber: clean
rm -f $(OBJS) *.bak tags TAGS
rm -fr *.*~
- rm -f armboot armboot.bin armboot.elf armboot.srec armboot.map
+ rm -f armboot armboot.bin armboot.elf armboot.srec armboot.map armboot.hex
rm -f tools/crc32.c tools/environment.S
mrproper \
CLEP7312 ep7312_config Cirrus Logic EP7312 Dev. Board
S3C2400X samsung_config Samsung S3C2400X
SMDK2410X smdk2410_config Samsung SMDK2410X Eval Board
-
+EPXA1DB epxa1db_config Altera EPXA1 Development Board
Testing of ARMBoot Modifications, Ports to New Hardware, etc.:
==============================================================
--- /dev/null
+#
+# Copyright (c) 2000-2002 Altera Corporation, San Jose, California, USA.
+# All rights reserved.
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+# If a full installation of Quartus isn't available, use the tools
+# supplied with armboot.
+
+ifndef QUARTUS_ROOTDIR
+QUARTUS_ROOTDIR = $(TOPDIR)/tools/quartus
+endif
+
+
+MAKEPROGFILE := $(QUARTUS_ROOTDIR)/bin/makeprogfile
+
+LIB = lib$(BOARD).a
+
+OBJS := epxa1db.o flash.o env.o mac_addr.o flash_int.o flash_amd.o
+
+EXC_CFG := excalibur.o
+
+all: $(LIB) $(EXC_CFG)
+
+$(LIB): $(OBJS)
+ $(AR) crv $@ $^
+
+$(EXC_CFG): quartus/excalibur.sbd
+ $(MAKEPROGFILE) -q -b $@ $<
+
+clean:
+ rm -f $(EXC_CFG) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- /dev/null
+
+Copyright (c) 2000-2002 Altera Corporation, San Jose, California, USA.
+All rights reserved.
+
+Overview
+========
+
+This README details Altera EPXA1 Development Board specific features of ARMboot. General
+ARMboot information can be found in the README file in the top level install directory.
+
+ARMboot for the epxa1db has been integrated into the Quartus toolflow so that the Altera
+Excalibur Mega-Wizard can be used to configure the Excalibur device. This provides a
+simple GUI based method for configuration of the device parameters (e.g. the physical
+memory map) to match the application requirements.
+
+This use of the Mega-Wizard is intended to ease porting of ARMboot to other boards which
+use Excalibur devices, and to ease porting between different members of the Excalibur
+family.
+
+The Quartus project used for ARMboot can be found in quartus/excalibur.quartus. Details of
+how to modify this project can be found in the online Quartus help. Alternatively you can
+contact Altera support at: support@altera.com.
+
+Installing Quartus
+==================
+
+In order to build ARMboot for the EPXA1 Development Board, you must install the Quartus
+tools. The environment variable 'QUARTUS_ROOTDIR' should be set to be the Quartus install
+directory.
+
+The minimum requirement is that you install the makeprogfile utility, which is used to parse
+the Mega-Wizard output:
+
+$QUARTUS_ROOTDIR/bin/makeprogfile
+
+and the Excalibur boot library:
+
+$QUARTUS_ROOTDIR/libraries/software/boot/libboot_xa_ads.a
+
+Building ARMboot for the EPXA1 Development Board
+================================================
+
+The following steps should be taken to configure and build ARMboot for the EPXA1 Development
+Board:
+
+1. Configure
+
+ sh# make epxa1db_config
+ rm -f include/config.h include/config.mk
+ Configuring for epxa1db Board...
+ ** See the README in board/epxa1db for build instructions **
+
+2. Build
+
+ sh# make all
+
+Further information can be found in the generic ARMboot README.
+
+Running ARMboot
+===============
+
+Having built ARMboot, the generated file, 'armboot.hex', can be programmed into the on board
+flash using the Altera flash programmer:
+
+ sh# exc_flash_programmer -g armboot.hex
+
+Serial output is available through serial connector 'P2', with: baud rate 115200, 8
+bits, 1 stop bit, no parity.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
--- /dev/null
+/*
+ * Copyright (c) 2000-2002 Altera Corporation, San Jose, California, USA.
+ * All rights reserved.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/epxa/start.o (.init)
+ *(.init)
+ board/epxa1db/excalibur.o
+ *(.text)
+ }
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = ALIGN(4);
+ .bss : { *(.bss) }
+
+ . = ALIGN(4);
+ armboot_end = .;
+}
--- /dev/null
+#
+# Copyright (c) 2000-2002 Altera Corporation, San Jose, California, USA.
+# All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to
+# deal in the Software without restriction, including without limitation the
+# rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+# sell copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+#
+# This agreement shall be governed in all respects by the laws of the State
+# of California and by the laws of the United States of America.
+#
+
+ifndef QUARTUS_ROOTDIR
+QUARTUS_ROOTDIR = $(TOPDIR)/tools/quartus
+endif
+
+CFLAGS += -g
+AFLAGS += -g
+TEXT_BASE = 0x00000
+
+EXTERN_LIB += $(QUARTUS_ROOTDIR)/libraries/software/boot/libboot_xa_ads.a
+
+LDFLAGS_EXTRA += -p
+
--- /dev/null
+/*
+ * Copyright (c) 2000-2002 Altera Corporation, San Jose, California, USA.
+ * All rights reserved.
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include "armboot.h"
+
+static int check_crc(bd_t *bd)
+{
+ /* need to calculate crc? */
+ if (bd->bi_ext.env_crc_valid == 0)
+ {
+ env_t *env = (env_t *)CFG_ENV_ADDR;
+
+ if (crc32(0, env->data, sizeof(env->data)) == env->crc)
+ bd->bi_ext.env_crc_valid = 1;
+ else
+ bd->bi_ext.env_crc_valid = -1;
+ }
+ return bd->bi_ext.env_crc_valid > 0;
+}
+
+
+/*
+ * save environment buffer back to flash
+ * returns -1 on error, 0 if ok
+ */
+int board_env_save(bd_t *bd, env_t *env, int size)
+{
+ int rc;
+ ulong start_addr, end_addr;
+
+#if CFG_ENV_SIZE <= CFG_ENV_SECT_SIZE
+#error Make sure that CFG_ENV_SIZE > CFG_ENV_SECT_SIZE
+#endif
+
+ start_addr = CFG_ENV_ADDR;
+ end_addr = start_addr + CFG_ENV_SIZE - 1;
+
+ rc = flash_sect_protect(0, CFG_ENV_ADDR, end_addr);
+ if (rc < 0)
+ return rc;
+
+ rc = flash_sect_erase(start_addr, end_addr);
+ if (rc < 0)
+ {
+ flash_sect_protect(1, start_addr, end_addr);
+ flash_perror(rc);
+ return rc;
+ }
+
+ printf("Saving Environment to Flash...");
+ rc = flash_write((uchar*)env, start_addr, size);
+ if (rc < 0)
+ flash_perror(rc);
+ else
+ printf("done.\n");
+
+ (void)flash_sect_protect(1, start_addr, end_addr);
+
+ return 0;
+}
+
+/*
+ * copy environment to memory
+ * returns -1 on error, 0 if ok
+ */
+int board_env_copy(bd_t *bd, env_t *data, int size)
+{
+ env_t *env = (env_t *)CFG_ENV_ADDR;
+
+ if (check_crc(bd))
+ {
+ memcpy(data, env, sizeof(env_t));
+ return 0;
+ }
+
+ return -1;
+}
+
+/*
+ * try to read env character at offset #index
+ *
+ * called before the environment is copied to ram
+ * returns -1 on error, 0 if ok
+ */
+int board_env_getchar(bd_t * bd, int index, uchar *c)
+{
+ env_t *env = (env_t *)CFG_ENV_ADDR;
+
+ /* check environment crc */
+ if (index < sizeof(env->data) && check_crc(bd))
+ {
+ *c = env->data[index];
+ return 0;
+ }
+
+ return -1;
+}
+
+/*
+ * try to read env character at offset #index
+ *
+ * called before the environment is copied to ram
+ * returns -1 on error, 0 if ok
+ */
+uchar *board_env_getaddr(bd_t * bd, int index)
+{
+ env_t *env = (env_t *)CFG_ENV_ADDR;
+
+ /* check environment crc */
+ if (index < sizeof(env->data) && check_crc(bd))
+ return &env->data[index];
+
+ return 0;
+}
+
+
+
+
+
+
+
+
+
+
--- /dev/null
+/*
+ * Copyright (c) 2000-2002 Altera Corporation, San Jose, California, USA.
+ * All rights reserved.
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include "armboot.h"
+#include "epxa/excalibur.h"
+
+extern void epxa1db_set_mac_addr(void);
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init(bd_t *bd)
+{
+ /* memory and cpu-speed are setup before relocation */
+ /* so nothing to do in that respect */
+
+ /* arch number of epxa1 Development Board */
+ bd->bi_arch_number = 0x62;
+
+ /* adress of boot parameters */
+ bd->bi_boot_params = 0x100;
+
+ return 1;
+}
+
+int dram_init(bd_t *bd)
+{
+ bd->bi_dram[0].start = EXC_SDRAM_BLOCK0_BASE;
+ bd->bi_dram[0].size = EXC_SDRAM_BLOCK0_SIZE;
+ return EXC_SDRAM_BLOCK0_SIZE;
+}
+
+
+
+
+
+
+
--- /dev/null
+/*
+ * Copyright (c) 2000-2002 Altera Corporation, San Jose, California, USA.
+ * All rights reserved.
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include "armboot.h"
+#include "config.h"
+#include "flash_amd.h"
+#include "flash_int.h"
+
+
+/* Default to Intel */
+void (*epxa_flash_print_info)(flash_info_t *info)=int_flash_print_info;
+int (*epxa_flash_erase) (flash_info_t *info, int s_first, int s_last)=int_flash_erase;
+int (*epxa_write_buff) (flash_info_t *info, uchar *src, ulong addr, ulong cnt)=int_write_buff;
+int (*epxa_flash_read_user)(int bank, int offset)=int_flash_read_user;
+
+typedef volatile unsigned short fltype;
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+#define PUZZLE_FROM_FLASH(x) (x)
+#define PUZZLE_TO_FLASH(x) (x)
+
+#define CMD_READ_ARRAY 0x00FF
+#define CMD_READ_CFI 0x0098
+
+
+/*-----------------------------------------------------------------------
+ */
+
+ulong flash_init(bd_t *bd)
+{
+
+ fltype *addr=(fltype*)(PHYS_FLASH_1+0xaa);
+ fltype val;
+
+
+ /* default is Intel Flash_devices, we'll assume that we've got
+ * One type or other and not one of each, so if the the first
+ * device proves not to be Intel then we'll assume that they're
+ * both AMD. If they're not then we don;t support them and we're
+ * knackered.
+ */
+
+
+ *addr = PUZZLE_TO_FLASH(CMD_READ_CFI);
+ val=PUZZLE_FROM_FLASH(*(fltype*)(PHYS_FLASH_1 + 0x26));
+ *addr = PUZZLE_TO_FLASH(CMD_READ_ARRAY);
+
+ if(val==3){
+ return int_flash_init(bd);
+ }else if(val==2){
+
+ /* its an AMD type thing */
+
+ epxa_flash_print_info=amd_flash_print_info;
+ epxa_flash_erase=amd_flash_erase;
+ epxa_write_buff=amd_write_buff;
+ epxa_flash_read_user=amd_flash_read_user;
+ return amd_flash_init(bd);
+ } else{
+ printf("Warning: unrecognised CFI command set:%d\n",val);
+ printf("Trying command set 3 instead, consider yourself lucky if it works\n");
+ return int_flash_init(bd);
+ }
+}
+void flash_print_info(flash_info_t *info){
+ epxa_flash_print_info(info);
+}
+
+int flash_erase(flash_info_t *info, int s_first, int s_last){
+ return epxa_flash_erase(info,s_first,s_last);
+}
+
+int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt){
+ return epxa_write_buff(info,src,addr,cnt);
+}
+
+int flash_read_user(int bank, int offset){
+ return epxa_flash_read_user(bank,offset);
+}
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include "armboot.h"
+
+ulong myflush(void);
+
+
+#define FLASH_BANK_SIZE 0x400000 /* 4 MB */
+#define MAIN_SECT_SIZE 0x10000
+#define PARAM_SECT_SIZE 0x1000
+
+extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+unsigned int flashbase[CFG_MAX_FLASH_BANKS]={
+ PHYS_FLASH_1,
+ PHYS_FLASH_2
+};
+
+#define CMD_READ_ARRAY 0x000000F0
+#define CMD_UNLOCK1 0x000000AA
+#define CMD_UNLOCK2 0x00000055
+#define CMD_ERASE_SETUP 0x00000080
+#define CMD_ERASE_CONFIRM 0x00000030
+#define CMD_PROGRAM 0x000000A0
+#define CMD_UNLOCK_BYPASS 0x00000020
+#define CMD_ENTER_SECSI 0x00000088
+#define CMD_EXIT_SECSI 0x00000090
+
+
+#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555 << 1)))
+#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA << 1)))
+//#define MEM_FLASH_ADDR1(base) (*(volatile u16 *)(base + (0x00000555<<1))
+//#define MEM_FLASH_ADDR2(base) (*(volatile u16 *)(base + (0x000002AA<<1))
+
+typedef volatile u16 fltype;
+
+#define BIT_ERASE_DONE 0x00000080
+#define BIT_RDY_MASK 0x00000080
+#define BIT_PROGRAM_ERROR 0x00000020
+#define BIT_TIMEOUT 0x80000000 /* our flag */
+
+#define READY 1
+#define ERR 2
+#define TMO 4
+
+/*-----------------------------------------------------------------------
+ */
+
+ulong amd_flash_init(bd_t *bd)
+{
+ int i, j;
+ ulong size = 0;
+
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; i++)
+ {
+ flash_info[i].flash_id =
+ (AMD_MANUFACT & FLASH_VENDMASK) |
+ (AMD_ID_DL322B & FLASH_TYPEMASK);
+ flash_info[i].size = FLASH_BANK_SIZE;
+ flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+ memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+ for (j = 0; j < flash_info[i].sector_count; j++)
+ {
+ if (j <= 7)
+ {
+ flash_info[i].start[j] = flashbase[i] + j * PARAM_SECT_SIZE;
+ }
+ else
+ {
+ flash_info[i].start[j] = flashbase[i] + (j - 7)*MAIN_SECT_SIZE;
+ }
+ }
+ size += flash_info[i].size;
+ }
+
+ /*
+ * Protect monitor and environment sectors
+ * Inferno is complicated, it's hardware locked
+ */
+#ifdef CONFIG_INFERNO
+ /* first one, 0x00000 to 0x07fff */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_FLASH_BASE + 0x00000,
+ CFG_FLASH_BASE + 0x08000 - 1,
+ &flash_info[0]);
+
+ /* third to 10th, 0x0c000 - 0xdffff */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_FLASH_BASE + 0x0c000,
+ CFG_FLASH_BASE + 0xe0000 - 1,
+ &flash_info[0]);
+#else
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_FLASH_BASE,
+ CFG_FLASH_BASE + _armboot_end - _armboot_start,
+ &flash_info[0]);
+
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+ &flash_info[0]);
+#endif
+ return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void amd_flash_print_info (flash_info_t *info)
+{
+ int i;
+
+ switch (info->flash_id & FLASH_VENDMASK)
+ {
+ case (AMD_MANUFACT & FLASH_VENDMASK):
+ printf("AMD: ");
+ break;
+ default:
+ printf("Unknown Vendor ");
+ break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK)
+ {
+ case (AMD_ID_LV160B & FLASH_TYPEMASK):
+ printf("2x Amd29F160BB (16Mbit)\n");
+ break;
+ case (AMD_ID_DL322B &FLASH_TYPEMASK):
+ printf("2x 29DL322B (32mBit)\n");
+ break;
+ default:
+ printf("Unknown Chip Type\n");
+ goto Done;
+ break;
+ }
+
+ printf(" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf(" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; i++)
+ {
+ if ((i % 5) == 0)
+ {
+ printf ("\n ");
+ }
+ printf (" %08lX%s", info->start[i],
+ info->protect[i] ? " (RO)" : " ");
+ }
+ printf ("\n");
+
+ Done:
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int amd_flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ ushort result;
+ int iflag, cflag, prot, sect;
+ int rc = ERR_OK;
+ int chip;
+
+ /* first look for protection bits */
+
+ if (info->flash_id == FLASH_UNKNOWN)
+ return ERR_UNKNOWN_FLASH_TYPE;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ return ERR_INVAL;
+ }
+
+ if ((info->flash_id & FLASH_VENDMASK) !=
+ (AMD_MANUFACT & FLASH_VENDMASK)) {
+ return ERR_UNKNOWN_FLASH_VENDOR;
+ }
+
+ prot = 0;
+ for (sect=s_first; sect<=s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+ if (prot)
+ return ERR_PROTECTED;
+
+ /*
+ * Disable interrupts which might cause a timeout
+ * here. Remember that our exception vectors are
+ * at address 0 in the flash, and we don't want a
+ * (ticker) exception to happen while the flash
+ * chip is in programming mode.
+ */
+ cflag = icache_status();
+ icache_disable();
+ iflag = disable_interrupts();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect<=s_last && !ctrlc(); sect++)
+ {
+ printf("Erasing sector %2d ... ", sect);
+
+ /* arm simple, non interrupt dependent timer */
+ reset_timer_masked();
+
+ if (info->protect[sect] == 0)
+ { /* not protected */
+ vushort *addr = (vushort *)(info->start[sect]);
+
+ MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+ MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+ MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
+
+ MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+ MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+ *addr = CMD_ERASE_CONFIRM;
+
+ /* wait until flash is ready */
+ chip = 0;
+
+ do
+ {
+ result = *addr;
+
+ /* check timeout */
+ if (get_timer_masked() > CFG_FLASH_ERASE_TOUT)
+ {
+ MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+ chip = TMO;
+ break;
+ }
+
+ if (!chip && (result & 0xFFFF) & BIT_ERASE_DONE)
+ chip = READY;
+
+ if (!chip && (result & 0xFFFF) & BIT_PROGRAM_ERROR)
+ chip = ERR;
+
+ } while (!chip);
+
+ MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+
+ if (chip == ERR)
+ {
+ rc = ERR_PROG_ERROR;
+ goto outahere;
+ }
+ if (chip == TMO)
+ {
+ rc = ERR_TIMOUT;
+ goto outahere;
+ }
+
+ printf("ok.\n");
+ }
+ else /* it was protected */
+ {
+ printf("protected!\n");
+ }
+ }
+
+ if (ctrlc())
+ printf("User Interrupt!\n");
+
+outahere:
+ /* allow flash to settle - wait 10 ms */
+ udelay_masked(10000);
+
+ if (iflag)
+ enable_interrupts();
+
+ if (cflag)
+ icache_enable();
+
+ return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash
+ */
+
+volatile static int write_hword (flash_info_t *info, ulong dest, ushort data)
+{
+ vushort *addr = (vushort *)dest;
+ ushort result;
+ int rc = ERR_OK;
+ int cflag, iflag;
+ int chip;
+
+ /*
+ * Check if Flash is (sufficiently) erased
+ */
+ result = *addr;
+ if ((result & data) != data)
+ return ERR_NOT_ERASED;
+
+
+ /*
+ * Disable interrupts which might cause a timeout
+ * here. Remember that our exception vectors are
+ * at address 0 in the flash, and we don't want a
+ * (ticker) exception to happen while the flash
+ * chip is in programming mode.
+ */
+ cflag = icache_status();
+ icache_disable();
+ iflag = disable_interrupts();
+
+ MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+ MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+// MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS;
+ MEM_FLASH_ADDR1 = CMD_PROGRAM;
+ *addr = data;
+
+ /* arm simple, non interrupt dependent timer */
+ reset_timer_masked();
+
+ /* wait until flash is ready */
+ chip = 0;
+ do
+ {
+ result = *addr;
+
+ /* check timeout */
+ if (get_timer_masked() > CFG_FLASH_ERASE_TOUT)
+ {
+ chip = ERR | TMO;
+ break;
+ }
+ if (!chip && ((result & 0x80) == (data & 0x80)))
+ chip = READY;
+
+ if (!chip && ((result & 0xFFFF) & BIT_PROGRAM_ERROR))
+ {
+ result = *addr;
+
+ if ((result & 0x80) == (data & 0x80))
+ chip = READY;
+ else
+ chip = ERR;
+ }
+
+ } while (!chip);
+
+
+ *addr = CMD_READ_ARRAY;
+
+ if (chip == ERR || *addr != data)
+ rc = ERR_PROG_ERROR;
+
+ if (iflag)
+ enable_interrupts();
+
+ if (cflag)
+ icache_enable();
+
+ return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int amd_write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong cp, wp;
+ int l;
+ int i, rc;
+ ushort data;
+
+ wp = (addr & ~1); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i=0, cp=wp; i<l; ++i, ++cp) {
+ data = (data >> 8) | (*(uchar *)cp << 8);
+ }
+ for (; i<2 && cnt>0; ++i) {
+ data = (data >> 8) | (*src++ << 8);
+ --cnt;
+ ++cp;
+ }
+ for (; cnt==0 && i<2; ++i, ++cp) {
+ data = (data >> 8) | (*(uchar *)cp << 8);
+ }
+
+ if ((rc = write_hword(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 2;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 2) {
+ data = *((vushort*)src);
+ if ((rc = write_hword(info, wp, data)) != 0) {
+ return (rc);
+ }
+ src += 2;
+ wp += 2;
+ cnt -= 2;
+ }
+
+ if (cnt == 0) {
+ return ERR_OK;
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) {
+ data = (data >> 8) | (*src++ << 8);
+ --cnt;
+ }
+ for (; i<2; ++i, ++cp) {
+ data = (data >> 8) | (*(uchar *)cp << 8);
+ }
+
+ return write_hword(info, wp, data);
+}
+
+int amd_flash_read_user(int bank, int offset){
+
+ fltype* addr;
+ int val;
+
+ if (bank == 1){
+ addr = (fltype*) PHYS_FLASH_1;
+ }
+ else if (bank == 2){
+ addr = (fltype*) PHYS_FLASH_2;
+ }
+ else{
+ return -1;
+ }
+ MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+ MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+ MEM_FLASH_ADDR1 = CMD_ENTER_SECSI;
+
+ val = *(addr + (offset >> 1));
+ if (offset & 0x1){
+ val >>= 8;
+ }
+ val &= 0xff;
+
+ MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+ MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+ MEM_FLASH_ADDR1 = CMD_EXIT_SECSI;
+ return val;
+
+
+}
--- /dev/null
+/*
+ * Copyright (c) 2002 Altera Corporation, San Jose, California, USA.
+ * All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+extern ulong amd_flash_init(bd_t *bd);
+extern void amd_flash_print_info(flash_info_t *info);
+extern int amd_flash_erase(flash_info_t *info, int s_first, int s_last);
+extern int amd_write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt);
+extern int amd_flash_read_user(int bank, int offset);
--- /dev/null
+/*
+ * Copyright (c) 2000-2002 Altera Corporation, San Jose, California, USA.
+ * All rights reserved.
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include "armboot.h"
+#include "config.h"
+
+ulong myflush(void);
+
+typedef volatile unsigned short fltype;
+
+#define FLASH_BANK_SIZE 0x400000
+#define MAIN_SECT_SIZE 0x10000
+#define PARAM_SECT_SIZE 0x2000
+
+#define PUZZLE_FROM_FLASH(x) (x)
+#define PUZZLE_TO_FLASH(x) (x)
+
+extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+#define CMD_READ_ARRAY 0x00FF
+#define CMD_IDENTIFY 0x0090
+#define CMD_ERASE_SETUP 0x0020
+#define CMD_ERASE_CONFIRM 0x00D0
+#define CMD_PROGRAM 0x0040
+#define CMD_RESUME 0x00D0
+#define CMD_SUSPEND 0x00B0
+#define CMD_STATUS_READ 0x0070
+#define CMD_STATUS_RESET 0x0050
+#define CMD_CONFIG_SETUP 0x0060
+#define CMD_LOCK_BLOCK 0x0001
+#define CMD_UNLOCK_BLOCK 0x00D0
+
+#define BIT_BUSY 0x0080
+#define BIT_ERASE_SUSPEND 0x0040
+#define BIT_ERASE_ERROR 0x0020
+#define BIT_PROGRAM_ERROR 0x0010
+#define BIT_VPP_RANGE_ERROR 0x0008
+#define BIT_PROGRAM_SUSPEND 0x0004
+#define BIT_PROTECT_ERROR 0x0002
+#define BIT_UNDEFINED 0x0001
+
+#define BIT_SEQUENCE_ERROR 0x0030
+#define BIT_TIMEOUT 0x8000
+
+#define MASK_VENDOR_ID 0xFF00FF00
+#define MASK_FLASHTYPE 0x00FF00FF
+
+/*-----------------------------------------------------------------------
+ */
+
+ulong int_flash_init(bd_t *bd)
+{
+ int i, j;
+ ulong size = 0;
+
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; i++)
+ {
+ ulong flashbase = 0;
+
+ flash_info[i].flash_id =
+ (INTEL_MANUFACT & FLASH_VENDMASK) |
+ (INTEL_ID_28F320C3B & FLASH_TYPEMASK);
+ flash_info[i].size = FLASH_BANK_SIZE;
+ flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+ memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+ if (i == 0)
+ flashbase = PHYS_FLASH_1;
+ else if (i == 1)
+ flashbase = PHYS_FLASH_2;
+// else
+// panic("configured to0 many flash banks!\n");
+
+
+
+ for (j = 0; j < flash_info[i].sector_count; j++)
+ {
+ if (j <= 7)
+ {
+ flash_info[i].start[j] = flashbase + j * PARAM_SECT_SIZE;
+ }
+ else
+ {
+ flash_info[i].start[j] = flashbase + (j - 7)*MAIN_SECT_SIZE;
+ }
+ }
+ size += flash_info[i].size;
+ }
+
+ /* Protect monitor and environment sectors
+ */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_FLASH_BASE,
+ CFG_FLASH_BASE + _armboot_end - _armboot_start,
+ &flash_info[0]);
+
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+ &flash_info[0]);
+
+ return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void int_flash_print_info (flash_info_t *info)
+{
+ int i;
+
+ switch (info->flash_id & FLASH_VENDMASK)
+ {
+ case (INTEL_MANUFACT & FLASH_VENDMASK):
+ printf("Intel: ");
+ break;
+ case (AMD_MANUFACT & FLASH_VENDMASK):
+ printf("AMD: ");
+ break;
+ default:
+ printf("Unknown Vendor ");
+ break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK)
+ {
+ case (INTEL_ID_28F160F3B & FLASH_TYPEMASK):
+ printf("2x 28F160F3B (16Mbit)\n");
+ break;
+ case (INTEL_ID_28F320C3B & FLASH_TYPEMASK):
+ printf("1x 28F320C3B (32Mbit)\n");
+ break;
+ case(AMD_ID_DL322B):
+ printf("1x 29DL322B ID (32 M, bottom boot sect)\n");
+ break;
+ default:
+ printf("Unknown Chip Type\n");
+ printf("flash id %#x\n",(int) info->flash_id);
+ goto Done;
+ break;
+ }
+
+ printf(" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf(" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; i++)
+ {
+ if ((i % 5) == 0)
+ {
+ printf ("\n ");
+ }
+ printf (" %08lX%s", info->start[i],
+ info->protect[i] ? " (RO)" : " ");
+ }
+ printf ("\n");
+
+ Done:
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+static int flash_error (ulong code)
+{
+ /* Check bit patterns */
+ /* SR.7=0 is busy, SR.7=1 is ready */
+ /* all other flags indicate error on 1 */
+ /* SR.0 is undefined */
+ /* Timeout is our faked flag */
+
+ /* sequence is described in Intel 290644-005 document */
+
+ /* check Timeout */
+ if (code & BIT_TIMEOUT)
+ {
+ printf ("Timeout\n");
+ return ERR_TIMOUT;
+ }
+
+ /* check Busy, SR.7 */
+ if (~code & BIT_BUSY)
+ {
+ printf ("Busy\n");
+ return ERR_PROG_ERROR;
+ }
+
+ /* check Vpp low, SR.3 */
+ if (code & BIT_VPP_RANGE_ERROR)
+ {
+ printf ("Vpp range error\n");
+ return ERR_PROG_ERROR;
+ }
+
+ /* check Device Protect Error, SR.1 */
+ if (code & BIT_PROTECT_ERROR)
+ {
+ printf ("Device protect error\n");
+ return ERR_PROG_ERROR;
+ }
+
+ /* check Command Seq Error, SR.4 & SR.5 */
+ if (code & BIT_SEQUENCE_ERROR)
+ {
+ printf ("Command seqence error\n");
+ return ERR_PROG_ERROR;
+ }
+
+ /* check Block Erase Error, SR.5 */
+ if (code & BIT_ERASE_ERROR)
+ {
+ printf ("Block erase error\n");
+ return ERR_PROG_ERROR;
+ }
+
+ /* check Program Error, SR.4 */
+ if (code & BIT_PROGRAM_ERROR)
+ {
+ printf ("Program error\n");
+ return ERR_PROG_ERROR;
+ }
+
+ /* check Block Erase Suspended, SR.6 */
+ if (code & BIT_ERASE_SUSPEND)
+ {
+ printf ("Block erase suspended\n");
+ return ERR_PROG_ERROR;
+ }
+
+ /* check Program Suspended, SR.2 */
+ if (code & BIT_PROGRAM_SUSPEND)
+ {
+ printf ("Program suspended\n");
+ return ERR_PROG_ERROR;
+ }
+
+ /* OK, no error */
+ return ERR_OK;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int int_flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ ulong result;
+ int iflag, cflag, prot, sect;
+ int rc = ERR_OK;
+
+ /* first look for protection bits */
+
+ if (info->flash_id == FLASH_UNKNOWN)
+ return ERR_UNKNOWN_FLASH_TYPE;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ return ERR_INVAL;
+ }
+
+ if ((info->flash_id & FLASH_VENDMASK) !=
+ (INTEL_MANUFACT & FLASH_VENDMASK)) {
+ return ERR_UNKNOWN_FLASH_VENDOR;
+ }
+
+ prot = 0;
+ for (sect=s_first; sect<=s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+ if (prot)
+ return ERR_PROTECTED;
+
+ /*
+ * Disable interrupts which might cause a timeout
+ * here. Remember that our exception vectors are
+ * at address 0 in the flash, and we don't want a
+ * (ticker) exception to happen while the flash
+ * chip is in programming mode.
+ */
+ cflag = icache_status();
+ icache_disable();
+ iflag = disable_interrupts();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect<=s_last && !ctrlc(); sect++)
+ {
+ printf("Erasing sector %2d ... ", sect);
+
+ /* arm simple, non interrupt dependent timer */
+ reset_timer_masked();
+
+ if (info->protect[sect] == 0)
+ { /* not protected */
+ fltype *addr = (fltype *)(info->start[sect]);
+
+ *addr = PUZZLE_TO_FLASH(CMD_CONFIG_SETUP);
+ *addr = PUZZLE_TO_FLASH(CMD_UNLOCK_BLOCK);
+ *addr = PUZZLE_TO_FLASH(CMD_STATUS_RESET);
+ *addr = PUZZLE_TO_FLASH(CMD_ERASE_SETUP);
+ *addr = PUZZLE_TO_FLASH(CMD_ERASE_CONFIRM);
+
+ /* wait until flash is ready */
+ do
+ {
+ /* check timeout */
+ if (get_timer_masked() > CFG_FLASH_ERASE_TOUT)
+ {
+ *addr = PUZZLE_TO_FLASH(CMD_SUSPEND);
+ result = BIT_TIMEOUT;
+ break;
+ }
+
+ result = PUZZLE_FROM_FLASH(*addr);
+ } while (~result & BIT_BUSY);
+
+ *addr = PUZZLE_TO_FLASH(CMD_CONFIG_SETUP);
+ *addr = PUZZLE_TO_FLASH(CMD_UNLOCK_BLOCK);
+ *addr = PUZZLE_TO_FLASH(CMD_READ_ARRAY);
+
+ if ((rc = flash_error(result)) != ERR_OK)
+ goto outahere;
+
+ printf("ok.\n");
+ }
+ else /* it was protected */
+ {
+ printf("protected!\n");
+ }
+ }
+
+ if (ctrlc())
+ printf("User Interrupt!\n");
+
+outahere:
+
+ /* allow flash to settle - wait 10 ms */
+ udelay_masked(10000);
+
+ if (iflag)
+ enable_interrupts();
+
+ if (cflag)
+ icache_enable();
+
+ return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash
+ */
+
+volatile static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+ fltype *addr = (fltype *)dest;
+ ulong result;
+ int rc = ERR_OK;
+ int cflag, iflag;
+
+ /* Check if Flash is (sufficiently) erased
+ */
+ result = PUZZLE_FROM_FLASH(*addr);
+ if ((result & data) != data)
+ return ERR_NOT_ERASED;
+
+ /*
+ * Disable interrupts which might cause a timeout
+ * here. Remember that our exception vectors are
+ * at address 0 in the flash, and we don't want a
+ * (ticker) exception to happen while the flash
+ * chip is in programming mode.
+ */
+ cflag = icache_status();
+ icache_disable();
+ iflag = disable_interrupts();
+
+ *addr = PUZZLE_TO_FLASH(CMD_STATUS_RESET);
+ *addr = PUZZLE_TO_FLASH(CMD_PROGRAM);
+ *addr = data;
+
+ /* arm simple, non interrupt dependent timer */
+ reset_timer_masked();
+
+ /* wait until flash is ready */
+ do
+ {
+ /* check timeout */
+ if (get_timer_masked() > CFG_FLASH_ERASE_TOUT)
+ {
+ *addr = PUZZLE_TO_FLASH(CMD_SUSPEND);
+ result = BIT_TIMEOUT;
+ break;
+ }
+
+ result = PUZZLE_FROM_FLASH(*addr);
+ } while (~result & BIT_BUSY);
+
+ *addr = PUZZLE_TO_FLASH(CMD_READ_ARRAY);
+
+ rc = flash_error(result);
+
+ if (iflag)
+ enable_interrupts();
+
+ if (cflag)
+ icache_enable();
+
+ return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int int_write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong wp, data, ep;
+ int l;
+ int rc;
+ int sec = 0;
+ int lsec;
+
+ wp = (addr & ~1); /* get lower half word aligned address */
+ ep = addr + cnt;
+
+ /* unlock all sectors being accessed */
+
+ while ((info->start[sec] < addr) && (++sec < info->sector_count));
+ sec--;
+
+ lsec = sec;
+
+ while ((sec < info->sector_count) && (info->start[sec] < ep)){
+ *((uchar *) info->start[sec]) = PUZZLE_TO_FLASH(CMD_CONFIG_SETUP);
+ *((uchar *) info->start[sec]) = PUZZLE_TO_FLASH(CMD_UNLOCK_BLOCK);
+ *((uchar *) info->start[sec++]) = PUZZLE_TO_FLASH(CMD_READ_ARRAY);
+ }
+
+ /*
+ * handle unaligned start bytes
+ */
+
+ if ((l = addr - wp) != 0) {
+ data = *(uchar *)wp | (*src++ << 8);
+ --cnt;
+
+ if ((rc = write_word(info, wp, data)) != 0) {
+ goto finish;
+ }
+ wp += 2;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 2) {
+ data = *((fltype*)src);
+ if ((rc = write_word(info, wp, data)) != 0) {
+ goto finish;
+ }
+ src += 2;
+ wp += 2;
+ cnt -= 2;
+ }
+
+ if (cnt == 0) {
+ rc = ERR_OK;
+ goto finish;
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+
+ data = ((*(uchar *)(wp + 1)) << 8) | *src;
+
+ rc = write_word(info, wp, data);
+
+ /* lock all sectors being accessed */
+
+finish:
+
+ while ((lsec < info->sector_count) && (info->start[lsec] < ep)){
+ *((uchar *) info->start[lsec]) = PUZZLE_TO_FLASH(CMD_CONFIG_SETUP);
+ *((uchar *) info->start[lsec]) = PUZZLE_TO_FLASH(CMD_UNLOCK_BLOCK);
+ *((uchar *) info->start[lsec++]) = PUZZLE_TO_FLASH(CMD_READ_ARRAY);
+ }
+ return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Read user data.
+ */
+
+int int_flash_read_user(int bank, int offset){
+ fltype* addr;
+ int val;
+
+ if (bank == 1){
+ addr = (fltype*) PHYS_FLASH_1;
+ }
+ else if (bank == 2){
+ addr = (fltype*) PHYS_FLASH_2;
+ }
+ else{
+ return -1;
+ }
+ *addr = PUZZLE_TO_FLASH(CMD_IDENTIFY);
+ val = *(addr + 0x85 + (offset >> 1));
+ if (offset & 0x1){
+ val >>= 8;
+ }
+ val &= 0xff;
+ *addr = PUZZLE_TO_FLASH(CMD_READ_ARRAY);
+ return val;
+}
+
--- /dev/null
+/*
+ * Copyright (c) 2002 Altera Corporation, San Jose, California, USA.
+ * All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+extern ulong int_flash_init(bd_t *bd);
+extern void int_flash_print_info(flash_info_t *info);
+extern int int_flash_erase(flash_info_t *info, int s_first, int s_last);
+extern int int_write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt);
+extern int int_flash_read_user(int bank, int offset);
--- /dev/null
+/*
+ * Copyright (c) 2000-2002 Altera Corporation, San Jose, California, USA.
+ * All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * This agreement shall be governed in all respects by the laws of the State
+ * of California and by the laws of the United States of America.
+ */
+
+#include "armboot.h"
+#include "command.h"
+#include "net.h"
+#include "epxa/excalibur.h"
+#include "../drivers/smc91111.h"
+
+extern char flash_read_user(int bank, int offset);
+
+/*
+ * epxa1db_set_mac_addr is called prior to the open function of the SMC network
+ * driver. It is used to obtain the mac address. If the environment variable
+ * 'ipaddr' has a value, that is the address used. Otherwise the
+ * address is calculated using the contents of flash.
+ *
+ */
+
+void epxa1db_set_mac_addr(bd_t* bd){
+
+ static const char vendor_id[2]={0x07,0xed};
+
+ char addr[6];
+ char buf[18];
+
+ char* s;
+ int i;
+ char* e;
+
+ /*
+ * if the mac address is defined in the environment, use that,
+ * otherwise derive it from the contents of flash.
+ */
+
+ s = getenv(bd, "ethaddr");
+
+ if (s) {
+ for (i=0; i<6; i++) {
+ addr[i] = s ? simple_strtoul(s, &e, 16) : 0;
+ if (s) s = (*e) ? e+1 : e;
+ }
+ }
+ else{
+
+ /* calculate the value using the flash contents */
+
+ addr[5] = (char) flash_read_user(1, 0);
+ addr[4] = (char) flash_read_user(1, 1);
+ addr[3] = 0;
+ addr[2] = vendor_id[1];
+ addr[1] = vendor_id[0];
+ addr[0] = 0;
+
+ /* update the environment */
+
+ sprintf(buf,"%x:%x:%x:%x:%x:%x", addr[0], addr[1], addr[2], addr[3],
+ addr[4], addr[5]);
+ setenv (bd, "ethaddr", buf);
+ }
+ smc_set_mac_addr(addr);
+}
+
+
+
+
+
+
+
+
--- /dev/null
+SOFTWARE_SETTINGS
+{
+ USE_C_PREPROCESSOR_FOR_GNU_ASM_FILES = ON;
+ DO_POST_BUILD_COMMAND_LINE = OFF;
+ PROGRAMMING_FILE_TYPE = "NO PROGRAMMING FILE";
+ OUTPUT_TYPE = "INTEL HEX";
+ TOOLSET = "CUSTOM BUILD";
+ BYTE_ORDER = "LITTLE ENDIAN";
+ PROCESSOR = ARM922T;
+}
--- /dev/null
+SOFTWARE_SETTINGS
+{
+ USE_C_PREPROCESSOR_FOR_GNU_ASM_FILES = ON;
+ DO_POST_BUILD_COMMAND_LINE = OFF;
+ PROGRAMMING_FILE_TYPE = "NO PROGRAMMING FILE";
+ OUTPUT_TYPE = "INTEL HEX";
+ TOOLSET = "CUSTOM BUILD";
+ BYTE_ORDER = "LITTLE ENDIAN";
+ PROCESSOR = ARM922T;
+}
--- /dev/null
+DEFAULT_DEVICE_OPTIONS
+{
+ GENERATE_CONFIG_HEXOUT_FILE = OFF;
+ GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON;
+ GENERATE_CONFIG_JBC_FILE = OFF;
+ GENERATE_CONFIG_JAM_FILE = OFF;
+ GENERATE_CONFIG_ISC_FILE = OFF;
+ GENERATE_CONFIG_SVF_FILE = OFF;
+ GENERATE_JBC_FILE_COMPRESSED = ON;
+ GENERATE_JBC_FILE = OFF;
+ GENERATE_JAM_FILE = OFF;
+ GENERATE_ISC_FILE = OFF;
+ GENERATE_SVF_FILE = OFF;
+ RESERVE_PIN = "AS INPUT TRI-STATED";
+ RESERVE_ALL_UNUSED_PINS = "AS OUTPUT DRIVING GROUND";
+ HEXOUT_FILE_COUNT_DIRECTION = UP;
+ HEXOUT_FILE_START_ADDRESS = 0;
+ GENERATE_HEX_FILE = OFF;
+ GENERATE_RBF_FILE = OFF;
+ GENERATE_TTF_FILE = OFF;
+ RESERVE_RUNLU_AFTER_CONFIGURATION = OFF;
+ RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED";
+ RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = OFF;
+ RESERVE_RDYNBUSY_AFTER_CONFIGURATION = OFF;
+ RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = OFF;
+ DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF;
+ AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON;
+ EPROM_USE_CHECKSUM_AS_USERCODE = OFF;
+ FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ STRATIX_CONFIGURATION_DEVICE = EPC2;
+ FLEX10K_CONFIGURATION_DEVICE = EPC2;
+ FLEX6K_CONFIGURATION_DEVICE = EPC1;
+ MERCURY_CONFIGURATION_DEVICE = EPC2;
+ EXCALIBUR_CONFIGURATION_DEVICE = EPC2;
+ APEX20K_CONFIGURATION_DEVICE = EPC2;
+ USE_CONFIGURATION_DEVICE = ON;
+ ENABLE_INIT_DONE_OUTPUT = OFF;
+ FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
+ ENABLE_DEVICE_WIDE_OE = OFF;
+ ENABLE_DEVICE_WIDE_RESET = OFF;
+ RELEASE_CLEARS_BEFORE_TRI_STATES = OFF;
+ AUTO_RESTART_CONFIGURATION = OFF;
+ ENABLE_VREFB_PIN = OFF;
+ ENABLE_VREFA_PIN = OFF;
+ SECURITY_BIT = OFF;
+ USER_START_UP_CLOCK = OFF;
+ APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ STRATIX_UPDATE_MODE = STANDARD;
+ USE_CHECKSUM_AS_USERCODE = OFF;
+ MAX7000_USE_CHECKSUM_AS_USERCODE = OFF;
+ MAX7000_JTAG_USER_CODE = FFFFFFFF;
+ FLEX10K_JTAG_USER_CODE = 7F;
+ MERCURY_JTAG_USER_CODE = FFFFFFFF;
+ APEX20K_JTAG_USER_CODE = FFFFFFFF;
+ STRATIX_JTAG_USER_CODE = FFFFFFFF;
+ RESERVE_NCEO_AFTER_CONFIGURATION = OFF;
+ FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
+ FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF;
+ ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
+ MAX7000_ENABLE_JTAG_BST_SUPPORT = ON;
+ ENABLE_JTAG_BST_SUPPORT = OFF;
+ CLOCK_DIVISOR = 1;
+ CLOCK_FREQUENCY = "10 MHZ";
+ CLOCK_SOURCE = INTERNAL;
+ COMPRESSION_MODE = OFF;
+}
+AUTO_SLD_HUB_ENTITY
+{
+ AUTO_INSERT_SLD_HUB_ENTITY = ENABLE;
+ HUB_INSTANCE_NAME = sld_hub_inst;
+ HUB_ENTITY_NAME = sld_hub;
+}
+CHIP(excalibur)
+{
+ DEVICE = AUTO;
+}
+COMPILER_SETTINGS
+{
+ DRC_FANOUT_EXCEEDING = 30;
+ DRC_REPORT_FANOUT_EXCEEDING = ON;
+ DRC_TOP_FANOUT = 50;
+ DRC_REPORT_TOP_FANOUT = ON;
+ RUN_DRC_DURING_COMPILATION = OFF;
+ ADV_NETLIST_OPT_RETIME_CORE_AND_IO = ON;
+ ADV_NETLIST_OPT_FIT_LE_DUPLICATION = OFF;
+ ADV_NETLIST_OPT_FIT_LE_RETIME = OFF;
+ ADV_NETLIST_OPT_SYNTH_GATE_RETIME = OFF;
+ ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP = OFF;
+ SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES = OFF;
+ SMART_COMPILE_STRATIX_PLLS = OFF;
+ RUN_TIMING_ANALYSES = ON;
+ MERGE_HEX_FILE = OFF;
+ FOCUS_ENTITY_NAME = |excalibur;
+ INITIAL_PLACEMENT_CONFIGURATION = 1;
+ FINAL_PLACEMENT_OPTIMIZATION = AUTOMATICALLY;
+ FAMILY = APEX20KE;
+ DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
+ DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
+ DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "LOWER TO 1ESB UPPER TO 1";
+ DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_DUAL_PORT_MODE_INPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
+ DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
+ DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
+ DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3";
+ DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3";
+ DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB";
+ DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB";
+ DPRAM_WIDE_MODE_OUTPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4ESB";
+ DPRAM_DEEP_MODE_OUTPUT_EPXA4_10 = "MEGALAB COLUMN 3";
+ DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
+ DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
+ DPRAM_WIDE_MODE_INPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4";
+ DPRAM_DEEP_MODE_INPUT_EPXA4_10 = "MEGALAB COLUMN 3";
+ DPRAM_OTHER_SIGNALS_EPXA4_10 = "DEFAULT OTHER ROUTING OPTIONS";
+ DPRAM_OUTPUT_EPXA4_10 = "DEFAULT OUTPUT ROUTING OPTIONS";
+ DPRAM_INPUT_EPXA4_10 = "DEFAULT INPUT ROUTING OPTIONS";
+ STRIPE_TO_PLD_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2";
+ PLD_TO_STRIPE_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2";
+ PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10 = "MEGALAB COLUMN 2";
+ STRIPE_TO_PLD_BRIDGE_EPXA4_10 = "MEGALAB COLUMN 1";
+ FAST_FIT_COMPILATION = OFF;
+ SIGNALPROBE_AUTO_ASSIGN = 0;
+ SIGNALPROBE_COMPILATION = OFF;
+ SIGNALPROBE_ROUTING = ALL_SIGNAL_PROBE;
+ LOGICLOCK_FITTER_TYPE = OFF;
+ OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING = ON;
+ OPTIMIZE_TIMING = NORMAL_COMPILATION;
+ COMPILATION_LEVEL = FULL;
+ SAVE_DISK_SPACE = ON;
+ SPEED_DISK_USAGE_TRADEOFF = NORMAL;
+ LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT = OFF;
+ SIGNALPROBE_ALLOW_OVERUSE = OFF;
+}
--- /dev/null
+/* megafunction wizard: %ARM-Based Excalibur%
+ GENERATION: STANDARD
+ VERSION: WM1.0
+ MODULE: ARM-Based Excalibur
+ PROJECT: excalibur
+ ============================================================
+ File Name: h:\data\excalibur\excalibur.h
+ Megafunction Name(s): ARM-Based Excalibur
+ ============================================================
+
+ ************************************************************
+ THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+ ************************************************************/
+
+#ifndef EXCALIBUR_H_INCLUDED
+#define EXCALIBUR_H_INCLUDED
+
+#define EXC_DEFINE_PROCESSOR_LITTLE_ENDIAN
+#define EXC_DEFINE_BOOT_FROM_FLASH
+
+#define EXC_INPUT_CLK_FREQUENCY (25000000)
+#define EXC_AHB1_CLK_FREQUENCY (160000000)
+#define EXC_AHB2_CLK_FREQUENCY (80000000)
+#define EXC_SDRAM_CLK_FREQUENCY (35341652)
+
+/* Registers Block */
+#define EXC_REGISTERS_BASE (0x7fffc000)
+#define EXC_MODE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x000)
+#define EXC_IO_CTRL00_BASE (EXC_REGISTERS_BASE + 0x040)
+#define EXC_MMAP00_BASE (EXC_REGISTERS_BASE + 0x080)
+#define EXC_PLD_CONFIG00_BASE (EXC_REGISTERS_BASE + 0x140)
+#define EXC_TIMER00_BASE (EXC_REGISTERS_BASE + 0x200)
+#define EXC_INT_CTRL00_BASE (EXC_REGISTERS_BASE + 0xc00)
+#define EXC_CLOCK_CTRL00_BASE (EXC_REGISTERS_BASE + 0x300)
+#define EXC_WATCHDOG00_BASE (EXC_REGISTERS_BASE + 0xa00)
+#define EXC_UART00_BASE (EXC_REGISTERS_BASE + 0x280)
+#define EXC_EBI00_BASE (EXC_REGISTERS_BASE + 0x380)
+#define EXC_SDRAM00_BASE (EXC_REGISTERS_BASE + 0x400)
+#define EXC_AHB12_BRIDGE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x800)
+#define EXC_PLD_STRIPE_BRIDGE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x100)
+#define EXC_STRIPE_PLD_BRIDGE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x100)
+
+#define EXC_REGISTERS_SIZE (0x00004000)
+
+/* EBI Block(s) */
+#define EXC_EBI_BLOCK0_BASE (0x40000000)
+#define EXC_EBI_BLOCK0_SIZE (0x00400000)
+#define EXC_EBI_BLOCK0_WIDTH (16)
+#define EXC_EBI_BLOCK0_NON_CACHEABLE
+#define EXC_EBI_BLOCK1_BASE (0x40400000)
+#define EXC_EBI_BLOCK1_SIZE (0x00400000)
+#define EXC_EBI_BLOCK1_WIDTH (16)
+#define EXC_EBI_BLOCK1_NON_CACHEABLE
+#define EXC_EBI_BLOCK3_BASE (0x40c00000)
+#define EXC_EBI_BLOCK3_SIZE (0x00400000)
+#define EXC_EBI_BLOCK3_WIDTH (16)
+#define EXC_EBI_BLOCK3_NON_CACHEABLE
+
+/* SDRAM Block(s) */
+#define EXC_SDRAM_BLOCK0_BASE (0x00000000)
+#define EXC_SDRAM_BLOCK0_SIZE (0x01000000)
+#define EXC_SDRAM_BLOCK0_WIDTH (16)
+
+/* Single Port SRAM Block(s) */
+#define EXC_SPSRAM_BLOCK0_BASE (0x20000000)
+#define EXC_SPSRAM_BLOCK0_SIZE (0x00004000)
+#define EXC_SPSRAM_BLOCK1_BASE (0x20020000)
+#define EXC_SPSRAM_BLOCK1_SIZE (0x00004000)
+
+/* Dual Port SRAM Block(s) */
+#define EXC_DPSRAM_BLOCK0_BASE (0x20040000)
+#define EXC_DPSRAM_BLOCK0_SIZE (0x00004000)
+#define EXC_DPSRAM_BLOCK0_WIDTH (0)
+
+/* PLD Block(s) */
+#define EXC_PLD_BLOCK0_BASE (0x80000000)
+#define EXC_PLD_BLOCK0_SIZE (0x80000000)
+#define EXC_PLD_BLOCK0_CACHEABLE
+#define EXC_PLD_BLOCK1_BASE (0x60000000)
+#define EXC_PLD_BLOCK1_SIZE (0x10000000)
+#define EXC_PLD_BLOCK1_NON_CACHEABLE
+
+#endif
--- /dev/null
+COMPILER_SETTINGS_LIST
+{
+ COMPILER_SETTINGS = excalibur;
+}
+SIMULATOR_SETTINGS_LIST
+{
+ SIMULATOR_SETTINGS = excalibur;
+}
+SOFTWARE_SETTINGS_LIST
+{
+ SOFTWARE_SETTINGS = Debug;
+ SOFTWARE_SETTINGS = Release;
+}
--- /dev/null
+; megafunction wizard: %ARM-Based Excalibur%
+; GENERATION: STANDARD
+; VERSION: WM1.0
+; MODULE: ARM-Based Excalibur
+; PROJECT: excalibur
+; ============================================================
+; File Name: h:\data\excalibur\excalibur.s
+; Megafunction Name(s): ARM-Based Excalibur
+; ============================================================
+
+; ************************************************************
+; THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+; ************************************************************
+
+EXC_DEFINE_PROCESSOR_LITTLE_ENDIAN EQU (1)
+EXC_DEFINE_PROCESSOR_BIG_ENDIAN EQU (0)
+
+EXC_DEFINE_BOOT_FROM_FLASH EQU (1)
+EXC_DEFINE_BOOT_FROM_SERIAL EQU (0)
+
+EXC_INPUT_CLK_FREQUENCY EQU (25000000)
+EXC_AHB1_CLK_FREQUENCY EQU (160000000)
+EXC_AHB2_CLK_FREQUENCY EQU (80000000)
+EXC_SDRAM_CLK_FREQUENCY EQU (35341652)
+
+; Registers Block
+EXC_REGISTERS_BASE EQU (0x7fffc000)
+EXC_MODE_CTRL00_BASE EQU (EXC_REGISTERS_BASE + 0x000)
+EXC_IO_CTRL00_BASE EQU (EXC_REGISTERS_BASE + 0x040)
+EXC_MMAP00_BASE EQU (EXC_REGISTERS_BASE + 0x080)
+EXC_PLD_CONFIG00_BASE EQU (EXC_REGISTERS_BASE + 0x140)
+EXC_TIMER00_BASE EQU (EXC_REGISTERS_BASE + 0x200)
+EXC_INT_CTRL00_BASE EQU (EXC_REGISTERS_BASE + 0xc00)
+EXC_CLOCK_CTRL00_BASE EQU (EXC_REGISTERS_BASE + 0x300)
+EXC_WATCHDOG00_BASE EQU (EXC_REGISTERS_BASE + 0xa00)
+EXC_UART00_BASE EQU (EXC_REGISTERS_BASE + 0x280)
+EXC_EBI00_BASE EQU (EXC_REGISTERS_BASE + 0x380)
+EXC_SDRAM00_BASE EQU (EXC_REGISTERS_BASE + 0x400)
+EXC_AHB12_BRIDGE_CTRL00_BASE EQU (EXC_REGISTERS_BASE + 0x800)
+EXC_PLD_STRIPE_BRIDGE_CTRL00_BASE EQU (EXC_REGISTERS_BASE + 0x100)
+EXC_STRIPE_PLD_BRIDGE_CTRL00_BASE EQU (EXC_REGISTERS_BASE + 0x100)
+
+EXC_REGISTERS_SIZE EQU (0x00004000)
+
+; EBI Block(s)
+EXC_EBI_BLOCK0_BASE EQU (0x40000000)
+EXC_EBI_BLOCK0_SIZE EQU (0x00400000)
+EXC_EBI_BLOCK0_WIDTH EQU (16)
+EXC_EBI_BLOCK0_NON_CACHEABLE EQU (1)
+EXC_EBI_BLOCK0_CACHEABLE EQU (0)
+EXC_EBI_BLOCK1_BASE EQU (0x40400000)
+EXC_EBI_BLOCK1_SIZE EQU (0x00400000)
+EXC_EBI_BLOCK1_WIDTH EQU (16)
+EXC_EBI_BLOCK1_NON_CACHEABLE EQU (1)
+EXC_EBI_BLOCK1_CACHEABLE EQU (0)
+EXC_EBI_BLOCK3_BASE EQU (0x40c00000)
+EXC_EBI_BLOCK3_SIZE EQU (0x00400000)
+EXC_EBI_BLOCK3_WIDTH EQU (16)
+EXC_EBI_BLOCK3_NON_CACHEABLE EQU (1)
+EXC_EBI_BLOCK3_CACHEABLE EQU (0)
+
+; SDRAM Block(s)
+EXC_SDRAM_BLOCK0_BASE EQU (0x00000000)
+EXC_SDRAM_BLOCK0_SIZE EQU (0x01000000)
+EXC_SDRAM_BLOCK0_WIDTH EQU (16)
+
+; Single Port SRAM Block(s)
+EXC_SPSRAM_BLOCK0_BASE EQU (0x20000000)
+EXC_SPSRAM_BLOCK0_SIZE EQU (0x00004000)
+EXC_SPSRAM_BLOCK1_BASE EQU (0x20020000)
+EXC_SPSRAM_BLOCK1_SIZE EQU (0x00004000)
+
+; Dual Port SRAM Block(s)
+EXC_DPSRAM_SEPERATE EQU (1)
+EXC_DPSRAM_COMBINED EQU (0)
+
+EXC_DPSRAM_BLOCK0_BASE EQU (0x20040000)
+EXC_DPSRAM_BLOCK0_SIZE EQU (0x00004000)
+EXC_DPSRAM_BLOCK0_WIDTH EQU (0)
+
+; PLD Block(s)
+EXC_PLD_BLOCK0_BASE EQU (0x80000000)
+EXC_PLD_BLOCK0_SIZE EQU (0x80000000)
+EXC_PLD_BLOCK0_CACHEABLE EQU (1)
+EXC_PLD_BLOCK0_NON_CACHEABLE EQU (0)
+EXC_PLD_BLOCK1_BASE EQU (0x60000000)
+EXC_PLD_BLOCK1_SIZE EQU (0x10000000)
+EXC_PLD_BLOCK1_NON_CACHEABLE EQU (1)
+EXC_PLD_BLOCK1_CACHEABLE EQU (0)
+
+ END
+
--- /dev/null
+device excalibur
+{
+ family = excalibur_arm;
+ type = epxa1;
+ quartus_version = "Version 2.1 Internal Build 151B 06/12/2002 SJ Full Version";
+ module excalibur
+ {
+ type = excalibur_stripe;
+ hold_processor = false;
+ boot_from_flash = true;
+ configuration_device = epc2;
+ programming_clock_frequency = 16000000;
+ endian = little;
+ parameters uart
+ {
+ enabled = true;
+ input_pin_standard = lvttl_3v3;
+ output_pin_standard = slow_slew;
+ }
+
+ parameters trace
+ {
+ enabled = false;
+ output_pin_standard = fast_slew;
+ }
+
+ parameters pld
+ {
+ use_pld_to_stripe_bridge = true;
+ use_stripe_to_pld_bridge = true;
+ use_pld_to_stripe_interrupts = false;
+ use_stripe_to_pld_interrupts = true;
+ use_debug_extensions = true;
+ use_trace_extensions = false;
+ use_gpio_port = false;
+ gpio_port_width = 4;
+ pld_to_stripe_interrupt_mode = Six_individual_requests;
+ }
+
+ parameters clocks
+ {
+ input_clock_frequency = 25000000;
+ desired_ahb1_clock_frequency = 160000000;
+ desired_sdram_clock_frequency = 133000000;
+ pll_ahb_bypass = false;
+ pll_ahb_m = 128;
+ pll_ahb_n = 5;
+ pll_ahb_k = 2;
+ ahb1_divide = 2;
+ ahb2_divide = 4;
+ pll_sdram_bypass = false;
+ pll_sdram_m = 234;
+ pll_sdram_n = 11;
+ pll_sdram_k = 2;
+ }
+
+ parameters dpram
+ {
+ combined_data_width = 32;
+ combined_address_range = 0x2000;
+ combined_mode = false;
+ combined_outputs_registered = false;
+ mode[0] = no_ports;
+ data_width[0] = 0;
+ address_range[0] = 0x0;
+ outputs_registered[0] = false;
+ region region[0]
+ {
+ address_base = 0x20040000;
+ enabled = true;
+ address_size = 0x4000;
+ }
+
+ mode[1] = no_ports;
+ data_width[1] = 0;
+ address_range[1] = 0x0;
+ outputs_registered[1] = false;
+ region region[1]
+ {
+ address_base = 0x140000;
+ enabled = false;
+ address_size = 0x0;
+ }
+
+ }
+
+ parameters sdram
+ {
+ input_pin_standard = lvttl_3v3;
+ output_pin_standard = fast_slew;
+ enabled = true;
+ data_width = 16;
+ type = SDR;
+ device_name = Custom;
+ active_to_read_or_write_delay = 15;
+ active_to_precharge_command = 37;
+ active_banka_to_bankb_command = 14;
+ precharge_command_period = 15;
+ write_recovery_time = 17;
+ active_to_active_command_period = 60;
+ refresh_period = 710;
+ auto_refresh_command_period = 66;
+ burst_length = 8;
+ row_address_bits = 13;
+ column_address_bits = 9;
+ bank_address_bits = 2;
+ cas_latency = 3.000000;
+ region region[0]
+ {
+ address_base = 0x0;
+ enabled = true;
+ address_size = 0x1000000;
+ }
+
+ region region[1]
+ {
+ address_base = 0x11000000;
+ enabled = false;
+ address_size = 0x0;
+ }
+
+ }
+
+ parameters ebi
+ {
+ input_pin_standard = lvttl_3v3;
+ output_pin_standard = slow_slew;
+ enabled = true;
+ clock_divide = 16;
+ timeout_enable = false;
+ timeout_clock_cycles = 1;
+ external_clock_enable = true;
+ split_read = false;
+ region region[0]
+ {
+ address_base = 0x40000000;
+ enabled = true;
+ address_size = 0x400000;
+ prefetch = false;
+ synchronous = true;
+ byte_enable = false;
+ wait_cycles = 10;
+ data_width = 16;
+ chip_select_polarity = low;
+ }
+
+ region region[1]
+ {
+ address_base = 0x40400000;
+ enabled = true;
+ address_size = 0x400000;
+ prefetch = false;
+ synchronous = true;
+ byte_enable = false;
+ wait_cycles = 10;
+ data_width = 16;
+ chip_select_polarity = low;
+ }
+
+ region region[2]
+ {
+ address_base = 0x40800000;
+ enabled = false;
+ address_size = 0x0;
+ prefetch = false;
+ synchronous = true;
+ byte_enable = false;
+ wait_cycles = 0;
+ data_width = 16;
+ chip_select_polarity = low;
+ }
+
+ region region[3]
+ {
+ address_base = 0x40C00000;
+ enabled = true;
+ address_size = 0x400000;
+ prefetch = false;
+ synchronous = true;
+ byte_enable = true;
+ wait_cycles = 15;
+ data_width = 16;
+ chip_select_polarity = low;
+ }
+
+ }
+
+ region registers
+ {
+ address_base = 0x7FFFC000;
+ enabled = true;
+ address_size = 0x4000;
+ }
+
+ region sram[0]
+ {
+ address_base = 0x20000000;
+ enabled = true;
+ address_size = 0x4000;
+ }
+
+ region sram[1]
+ {
+ address_base = 0x20020000;
+ enabled = true;
+ address_size = 0x4000;
+ }
+
+ region pld[0]
+ {
+ address_base = 0x80000000;
+ enabled = true;
+ address_size = 0x80000000;
+ prefetch = true;
+ }
+
+ region pld[1]
+ {
+ address_base = 0x60000000;
+ enabled = true;
+ address_size = 0x10000000;
+ prefetch = false;
+ }
+
+ region pld[2]
+ {
+ address_base = 0x0;
+ enabled = false;
+ address_size = 0x0;
+ prefetch = false;
+ }
+
+ region pld[3]
+ {
+ address_base = 0x0;
+ enabled = false;
+ address_size = 0x0;
+ prefetch = false;
+ }
+
+ }
+
+}
+
--- /dev/null
+// megafunction wizard: %ARM-Based Excalibur%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: ARM-Based Excalibur
+// PROJECT: excalibur
+// ============================================================
+// File Name: h:\data\excalibur\excalibur.v
+// Megafunction Name(s): ARM-Based Excalibur
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+// ************************************************************
+//
+// Copyright (C) 1991-2002 Altera Corporation
+// Any megafunction design, and related netlist (encrypted or decrypted),
+// support information, device programming or simulation file, and any other
+// associated documentation or information provided by Altera or a partner
+// under Altera's Megafunction Partnership Program may be used only
+// to program PLD devices (but not masked PLD devices) from Altera. Any
+// other use of such megafunction design, netlist, support information,
+// device programming or simulation file, or any other related documentation
+// or information is prohibited for any other purpose, including, but not
+// limited to modification, reverse engineering, de-compiling, or use with
+// any other silicon devices, unless such use is explicitly licensed under
+// a separate agreement with Altera or a megafunction partner. Title to the
+// intellectual property, including patents, copyrights, trademarks, trade
+// secrets, or maskworks, embodied in any such megafunction design, netlist,
+// support information, device programming or simulation file, or any other
+// related documentation or information provided by Altera or a megafunction
+// partner, remains with Altera, the megafunction partner, or their respective
+// licensors. No other licenses, including any licenses needed under any third
+// party's intellectual property, are provided herein.
+//
+
+module excalibur
+(
+ clk_ref,
+ npor,
+ nreset,
+ uartrxd,
+ uartdsrn,
+ uartctsn,
+ uartrin,
+ uartdcdn,
+ uarttxd,
+ uartrtsn,
+ uartdtrn,
+ intextpin,
+ ebiack,
+ ebidq,
+ ebiclk,
+ ebiwen,
+ ebioen,
+ ebiaddr,
+ ebibe,
+ ebicsn,
+ sdramdq,
+ sdramdqs,
+ sdramclk,
+ sdramclkn,
+ sdramclke,
+ sdramwen,
+ sdramcasn,
+ sdramrasn,
+ sdramaddr,
+ sdramcsn,
+ sdramdqm,
+ slavehclk,
+ slavehwrite,
+ slavehreadyi,
+ slavehselreg,
+ slavehsel,
+ slavehmastlock,
+ slavehaddr,
+ slavehtrans,
+ slavehsize,
+ slavehburst,
+ slavehwdata,
+ slavehreadyo,
+ slavebuserrint,
+ slavehresp,
+ slavehrdata,
+ masterhclk,
+ masterhready,
+ masterhgrant,
+ masterhrdata,
+ masterhresp,
+ masterhwrite,
+ masterhlock,
+ masterhbusreq,
+ masterhaddr,
+ masterhburst,
+ masterhsize,
+ masterhtrans,
+ masterhwdata,
+ intuart,
+ inttimer0,
+ inttimer1,
+ intcommtx,
+ intcommrx,
+ debugrq,
+ debugext0,
+ debugext1,
+ debugextin,
+ debugack,
+ debugrng0,
+ debugrng1,
+ debugextout
+);
+
+input clk_ref;
+input npor;
+inout nreset;
+input uartrxd;
+input uartdsrn;
+input uartctsn;
+inout uartrin;
+inout uartdcdn;
+output uarttxd;
+output uartrtsn;
+output uartdtrn;
+input intextpin;
+input ebiack;
+inout [15:0] ebidq;
+output ebiclk;
+output ebiwen;
+output ebioen;
+output [24:0] ebiaddr;
+output [1:0] ebibe;
+output [3:0] ebicsn;
+inout [15:0] sdramdq;
+inout [1:0] sdramdqs;
+output sdramclk;
+output sdramclkn;
+output sdramclke;
+output sdramwen;
+output sdramcasn;
+output sdramrasn;
+output [14:0] sdramaddr;
+output [1:0] sdramcsn;
+output [1:0] sdramdqm;
+input slavehclk;
+input slavehwrite;
+input slavehreadyi;
+input slavehselreg;
+input slavehsel;
+input slavehmastlock;
+input [31:0] slavehaddr;
+input [1:0] slavehtrans;
+input [1:0] slavehsize;
+input [2:0] slavehburst;
+input [31:0] slavehwdata;
+output slavehreadyo;
+output slavebuserrint;
+output [1:0] slavehresp;
+output [31:0] slavehrdata;
+input masterhclk;
+input masterhready;
+input masterhgrant;
+input [31:0] masterhrdata;
+input [1:0] masterhresp;
+output masterhwrite;
+output masterhlock;
+output masterhbusreq;
+output [31:0] masterhaddr;
+output [2:0] masterhburst;
+output [1:0] masterhsize;
+output [1:0] masterhtrans;
+output [31:0] masterhwdata;
+output intuart;
+output inttimer0;
+output inttimer1;
+output intcommtx;
+output intcommrx;
+input debugrq;
+input debugext0;
+input debugext1;
+input [3:0] debugextin;
+output debugack;
+output debugrng0;
+output debugrng1;
+output [3:0] debugextout;
+
+wire proc_ntrst;
+wire proc_tck;
+wire proc_tdi;
+wire proc_tms;
+wire proc_tdo;
+wire [5:0] intpld;
+
+assign proc_ntrst = 1'b1;
+assign proc_tck = 1'b0;
+assign proc_tdi = 1'b0;
+assign proc_tms = 1'b0;
+assign intpld = 6'b0;
+
+alt_exc_stripe lpm_instance
+(
+ .clk_ref(clk_ref),
+ .npor(npor),
+ .nreset(nreset),
+ .uartrxd(uartrxd),
+ .uartdsrn(uartdsrn),
+ .uartctsn(uartctsn),
+ .uartrin(uartrin),
+ .uartdcdn(uartdcdn),
+ .uarttxd(uarttxd),
+ .uartrtsn(uartrtsn),
+ .uartdtrn(uartdtrn),
+ .intextpin(intextpin),
+ .ebiack(ebiack),
+ .ebidq(ebidq),
+ .ebiclk(ebiclk),
+ .ebiwen(ebiwen),
+ .ebioen(ebioen),
+ .ebiaddr(ebiaddr),
+ .ebibe(ebibe),
+ .ebicsn(ebicsn),
+ .sdramdq(sdramdq),
+ .sdramdqs(sdramdqs),
+ .sdramclk(sdramclk),
+ .sdramclkn(sdramclkn),
+ .sdramclke(sdramclke),
+ .sdramwen(sdramwen),
+ .sdramcasn(sdramcasn),
+ .sdramrasn(sdramrasn),
+ .sdramaddr(sdramaddr),
+ .sdramcsn(sdramcsn),
+ .sdramdqm(sdramdqm),
+ .slavehclk(slavehclk),
+ .slavehwrite(slavehwrite),
+ .slavehreadyi(slavehreadyi),
+ .slavehselreg(slavehselreg),
+ .slavehsel(slavehsel),
+ .slavehmastlock(slavehmastlock),
+ .slavehaddr(slavehaddr),
+ .slavehtrans(slavehtrans),
+ .slavehsize(slavehsize),
+ .slavehburst(slavehburst),
+ .slavehwdata(slavehwdata),
+ .slavehreadyo(slavehreadyo),
+ .slavebuserrint(slavebuserrint),
+ .slavehresp(slavehresp),
+ .slavehrdata(slavehrdata),
+ .masterhclk(masterhclk),
+ .masterhready(masterhready),
+ .masterhgrant(masterhgrant),
+ .masterhrdata(masterhrdata),
+ .masterhresp(masterhresp),
+ .masterhwrite(masterhwrite),
+ .masterhlock(masterhlock),
+ .masterhbusreq(masterhbusreq),
+ .masterhaddr(masterhaddr),
+ .masterhburst(masterhburst),
+ .masterhsize(masterhsize),
+ .masterhtrans(masterhtrans),
+ .masterhwdata(masterhwdata),
+ .intuart(intuart),
+ .inttimer0(inttimer0),
+ .inttimer1(inttimer1),
+ .intcommtx(intcommtx),
+ .intcommrx(intcommrx),
+ .debugrq(debugrq),
+ .debugext0(debugext0),
+ .debugext1(debugext1),
+ .debugextin(debugextin),
+ .debugack(debugack),
+ .debugrng0(debugrng0),
+ .debugrng1(debugrng1),
+ .debugextout(debugextout),
+ .proc_ntrst(proc_ntrst),
+ .proc_tck(proc_tck),
+ .proc_tdi(proc_tdi),
+ .proc_tms(proc_tms),
+ .proc_tdo(proc_tdo),
+ .intpld(intpld)
+);
+defparam
+ lpm_instance.sdram_width = 16,
+ lpm_instance.sdramdqm_width = 2,
+ lpm_instance.processor = "ARM",
+ lpm_instance.device_size = 100,
+ lpm_instance.boot_from_flash = "TRUE",
+ lpm_instance.debug_extensions = "TRUE",
+ lpm_instance.ebi0_width = 16,
+ lpm_instance.use_initialisation_files = "TRUE",
+ lpm_instance.use_short_reset = "TRUE",
+ lpm_instance.dp0_output_mode = "UNREG",
+ lpm_instance.dp1_output_mode = "UNREG",
+ lpm_instance.dp0_mode = "UNUSED",
+ lpm_instance.dp1_mode = "UNUSED";
+
+endmodule
--- /dev/null
+[Web SPR Info]\r
+Version=2.1\r
+Product=Quartus II\r
endif
COBJS = board.o main.o command.o \
cmd_boot.o cmd_bootm.o cmd_cache.o \
- cmd_eeprom.o cmd_ide.o cmd_pcmcia.o \
+ cmd_eeprom.o \
cmd_flash.o cmd_mem.o cmd_net.o \
cmd_nvedit.o cmd_autoscript.o cmd_misc.o cmd_jffs2.o \
s_record.o dlmalloc.o \
OBJS = $(AOBJS) $(COBJS)
+ifneq ($(BOARD),epxa1db)
+COBJS += cmd_ide.o cmd_pcmcia.o
+endif
+
CPPFLAGS += -I..
all: $(LIB) $(AOBJS)
extern void cs8900_get_enetaddr(uchar *addr);
#endif
+#ifdef CONFIG_EPXA1DB_MAC_ADDR
+extern void epxa1db_set_mac_addr(bd_t* bd);
+#endif
+
/*
* Begin and End of memory area for malloc(), and current "brk"
*/
/* enable exceptions */
enable_interrupts();
+
+/*
+ * FIXME: this should probably be rationalised into a standard call for
+ * each board, e.g. enet_mac_init() - but this'll do for now.
+ */
#ifdef CONFIG_DRIVER_CS8900
if (!getenv(&bd,"ethaddr") ) {
cs8900_get_enetaddr(bd.bi_enetaddr);
}
-#endif
+#endif
+
+#ifdef CONFIG_EPXA1DB_MAC_ADDR
+ epxa1db_set_mac_addr(&bd);
+#endif
+
/* main_loop() can return to retry autoboot, if so just run it again. */
for (;;) {
main_loop(&bd);
--- /dev/null
+#
+# Copyright (c) 2000-2002 Altera Corporation, San Jose, California, USA.
+# All rights reserved.
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(CPU).a
+
+START = start.o
+OBJS = serial.o interrupts.o cpu.o
+
+all: .depend $(START) $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+#
+# Copyright (c) 2000-2002 Altera Corporation, San Jose, California, USA.
+# All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to
+# deal in the Software without restriction, including without limitation the
+# rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+# sell copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+#
+# This agreement shall be governed in all respects by the laws of the State
+# of California and by the laws of the United States of America.
+#
+
+PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common \
+ -mshort-load-bytes -msoft-float
+
+PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4
+
+
+
+
+
+
+
--- /dev/null
+/*
+ * Copyright (c) 2000-2002 Altera Corporation, San Jose, California, USA.
+ * All rights reserved.
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * CPU specific code
+ */
+
+#include "armboot.h"
+#include "command.h"
+
+void cpu_init(bd_t *bd)
+{
+ /*
+ * setup up stack if necessary
+ */
+
+#ifdef CONFIG_USE_IRQ
+ IRQ_STACK_START = _armboot_end +
+ CONFIG_STACKSIZE + CONFIG_STACKSIZE_IRQ - 4;
+ FIQ_STACK_START = IRQ_STACK_START + CONFIG_STACKSIZE_FIQ;
+ _armboot_real_end = FIQ_STACK_START + 4;
+#else
+ _armboot_real_end = _armboot_end + CONFIG_STACKSIZE;
+#endif
+}
+
+void cleanup_before_linux(bd_t *bd)
+{
+ /*
+ * this function is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * just disable everything that can disturb booting linux
+ */
+
+ unsigned long i;
+
+ disable_interrupts();
+
+ /* turn off I-cache */
+ asm ("mrc p15, 0, %0, c1, c0, 0": "=r" (i));
+ i &= ~0x1000;
+ asm ("mcr p15, 0, %0, c1, c0, 0": : "r" (i));
+
+ /* flush I-cache */
+ asm ("mcr p15, 0, %0, c7, c5, 0": : "r" (i));
+}
+
+void do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+ extern void reset_cpu(ulong addr);
+
+ printf("reseting ...\n");
+
+ udelay(50000); /* wait 50 ms */
+ disable_interrupts();
+ reset_cpu(0);
+ /*NOTREACHED*/
+}
+
+/* taken from blob */
+void icache_enable(void)
+{
+ register u32 i;
+
+ /* read control register */
+ asm ("mrc p15, 0, %0, c1, c0, 0": "=r" (i));
+
+ /* set i-cache */
+ i |= 0x1000;
+
+ /* write back to control register */
+ asm ("mcr p15, 0, %0, c1, c0, 0": : "r" (i));
+}
+
+void icache_disable(void)
+{
+ register u32 i;
+
+ /* read control register */
+ asm ("mrc p15, 0, %0, c1, c0, 0": "=r" (i));
+
+ /* clear i-cache */
+ i &= ~0x1000;
+
+ /* write back to control register */
+ asm ("mcr p15, 0, %0, c1, c0, 0": : "r" (i));
+
+ /* flush i-cache */
+ asm ("mcr p15, 0, %0, c7, c5, 0": : "r" (i));
+}
+
+int icache_status(void)
+{
+ register u32 i;
+
+ /* read control register */
+ asm ("mrc p15, 0, %0, c1, c0, 0": "=r" (i));
+
+ /* return bit */
+ return (i & 0x1000);
+}
+
+/* we will never enable dcache, because we have to setup MMU first */
+void dcache_enable(void)
+{
+ return;
+}
+
+void dcache_disable(void)
+{
+ return;
+}
+
+int dcache_status(void)
+{
+ return 0; /* always off */
+}
+
--- /dev/null
+/*
+ * Copyright (c) 2000-2002 Altera Corporation, San Jose, California, USA.
+ * All rights reserved.
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include "armboot.h"
+#include "ptregs.h"
+#include "epxa/timer00.h"
+#include "epxa/excalibur.h"
+#define TIMER00_TYPE (volatile unsigned int*)
+
+extern void reset_cpu(ulong addr);
+
+#ifdef CONFIG_USE_IRQ
+/* enable IRQ/FIQ interrupts */
+void enable_interrupts (void)
+{
+ unsigned long temp;
+ __asm__ __volatile__("mrs %0, cpsr\n"
+ "bic %0, %0, #0x80\n"
+ "msr cpsr_c, %0"
+ : "=r" (temp)
+ :
+ : "memory");
+}
+
+
+/*
+ * disable IRQ/FIQ interrupts
+ * returns true if interrupts had been enabled before we disabled them
+ */
+int disable_interrupts (void)
+{
+ unsigned long old,temp;
+ __asm__ __volatile__("mrs %0, cpsr\n"
+ "orr %1, %0, #0x80\n"
+ "msr cpsr_c, %1"
+ : "=r" (old), "=r" (temp)
+ :
+ : "memory");
+ return (old & 0x80) == 0;
+}
+#else
+void enable_interrupts (void)
+{
+ return;
+}
+int disable_interrupts (void)
+{
+ return 0;
+}
+#endif
+
+
+
+void bad_mode(void)
+{
+ panic("Resetting CPU ...\n");
+ reset_cpu(0);
+}
+
+void show_regs(struct pt_regs * regs)
+{
+ unsigned long flags;
+const char *processor_modes[]=
+{ "USER_26", "FIQ_26" , "IRQ_26" , "SVC_26" , "UK4_26" , "UK5_26" , "UK6_26" , "UK7_26" ,
+ "UK8_26" , "UK9_26" , "UK10_26", "UK11_26", "UK12_26", "UK13_26", "UK14_26", "UK15_26",
+ "USER_32", "FIQ_32" , "IRQ_32" , "SVC_32" , "UK4_32" , "UK5_32" , "UK6_32" , "ABT_32" ,
+ "UK8_32" , "UK9_32" , "UK10_32", "UND_32" , "UK12_32", "UK13_32", "UK14_32", "SYS_32"
+};
+
+ flags = condition_codes(regs);
+
+ printf("pc : [<%08lx>] lr : [<%08lx>]\n"
+ "sp : %08lx ip : %08lx fp : %08lx\n",
+ instruction_pointer(regs),
+ regs->ARM_lr, regs->ARM_sp,
+ regs->ARM_ip, regs->ARM_fp);
+ printf("r10: %08lx r9 : %08lx r8 : %08lx\n",
+ regs->ARM_r10, regs->ARM_r9,
+ regs->ARM_r8);
+ printf("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",
+ regs->ARM_r7, regs->ARM_r6,
+ regs->ARM_r5, regs->ARM_r4);
+ printf("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n",
+ regs->ARM_r3, regs->ARM_r2,
+ regs->ARM_r1, regs->ARM_r0);
+ printf("Flags: %c%c%c%c",
+ flags & CC_N_BIT ? 'N' : 'n',
+ flags & CC_Z_BIT ? 'Z' : 'z',
+ flags & CC_C_BIT ? 'C' : 'c',
+ flags & CC_V_BIT ? 'V' : 'v');
+ printf(" IRQs %s FIQs %s Mode %s%s\n",
+ interrupts_enabled(regs) ? "on" : "off",
+ fast_interrupts_enabled(regs) ? "on" : "off",
+ processor_modes[processor_mode(regs)],
+ thumb_mode(regs) ? " (T)" : "");
+}
+
+void do_undefined_instruction(struct pt_regs *pt_regs)
+{
+ printf("undefined instruction\n");
+ show_regs(pt_regs);
+ bad_mode();
+}
+
+void do_software_interrupt(struct pt_regs *pt_regs)
+{
+ printf("software interrupt\n");
+ show_regs(pt_regs);
+ bad_mode();
+}
+
+void do_prefetch_abort(struct pt_regs *pt_regs)
+{
+ printf("prefetch abort\n");
+ show_regs(pt_regs);
+ bad_mode();
+}
+
+void do_data_abort(struct pt_regs *pt_regs)
+{
+ printf("data abort\n");
+ show_regs(pt_regs);
+ bad_mode();
+}
+
+void do_not_used(struct pt_regs *pt_regs)
+{
+ printf("not used\n");
+ show_regs(pt_regs);
+ bad_mode();
+}
+
+void do_fiq(struct pt_regs *pt_regs)
+{
+ printf("fast interrupt request\n");
+ show_regs(pt_regs);
+ bad_mode();
+}
+
+void do_irq(struct pt_regs *pt_regs)
+{
+ printf("interrupt request\n");
+ show_regs(pt_regs);
+ bad_mode();
+}
+
+
+extern void interrupt_init (bd_t *bd)
+{
+ /* nothing happens here - we don't setup any IRQs */
+}
+
+void reset_timer (void)
+{
+ reset_timer_masked ();
+}
+
+ulong get_timer (ulong base)
+{
+ return get_timer_masked();
+}
+
+void set_timer (ulong t)
+{
+ /* nop */
+}
+
+void udelay(unsigned long usec)
+{
+ udelay_masked(usec);
+}
+
+void reset_timer_masked(void)
+{
+ *TIMER0_CR(EXC_TIMER00_BASE)=0;
+ *TIMER0_PRESCALE(EXC_TIMER00_BASE)=0;
+ *TIMER0_LIMIT(EXC_TIMER00_BASE)=0XFFFFFFFF;
+ *TIMER0_CR(EXC_TIMER00_BASE)=TIMER0_CR_MODE_FREE|TIMER0_CR_S_MSK;
+}
+
+ulong get_timer_masked(void)
+{
+ return *TIMER0_READ(EXC_TIMER00_BASE);
+}
+
+
+
+void udelay_masked(unsigned long usec)
+{
+ reset_timer_masked();
+ while(get_timer_masked()<(usec*(EXC_AHB2_CLK_FREQUENCY/1000000)));
+}
+
+
--- /dev/null
+/*
+ * Copyright (c) 2000-2002 Altera Corporation, San Jose, California, USA.
+ * All rights reserved.
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include "armboot.h"
+#define UART00_TYPE (volatile unsigned int*)
+#include "epxa/uart00.h"
+#include "epxa/excalibur.h"
+
+#define DIVISOR_FROM_BAUD(baud,clk) ((clk) /(16*(baud)))
+
+
+void serial_setbrg(bd_t *bd, int baudrate)
+{
+ /*
+ * configure the uart for 38400 baud, 8 data,
+ * 1 stop, no parity
+ */
+
+ *UART_MC(EXC_UART00_BASE) = UART_MC_CLS_CHARLEN_8;
+ *UART_DIV_LO(EXC_UART00_BASE) = DIVISOR_FROM_BAUD(baudrate,EXC_AHB2_CLK_FREQUENCY)& 0xFF;
+ *UART_DIV_HI(EXC_UART00_BASE) = (DIVISOR_FROM_BAUD(baudrate,EXC_AHB2_CLK_FREQUENCY)& 0xFF00) >> 8;
+
+
+}
+
+
+/*
+ * Initialise the serial port with the given baudrate. The settings
+ * are always 8 data bits, no parity, 1 stop bit, no start bits.
+ *
+ */
+void serial_init(bd_t *bd)
+{
+ const char *baudrate;
+
+ if ((baudrate = getenv(bd, "baudrate")) != 0)
+ bd->bi_baudrate = simple_strtoul(baudrate, NULL, 10);
+
+ serial_setbrg(bd, bd->bi_baudrate);
+ /* Setup and clear FIFOs */
+ *UART_FCR(EXC_UART00_BASE)=UART_FCR_RX_THR_1 | UART_FCR_TX_THR_15 |
+ UART_FCR_RC_MSK | UART_FCR_TC_MSK;
+}
+
+
+/*
+ * Output a single byte to the serial port.
+ */
+void serial_putc(const char c)
+{
+ /* Wait for space in the fifo */
+ while(((*UART_TSR(EXC_UART00_BASE) & UART_TSR_TX_LEVEL_MSK)==15));
+
+ *UART_TD(EXC_UART00_BASE)=c;
+
+ /* If \n, also do \r */
+ if(c == '\n')
+ serial_putc('\r');
+}
+
+/*
+ * Read a single byte from the serial port. Returns 1 on success, 0
+ * otherwise. When the function is succesfull, the character read is
+ * written into its argument c.
+ */
+int serial_tstc(void)
+{
+
+ if(*UART_RSR(EXC_UART00_BASE) & UART_RSR_RX_LEVEL_MSK){
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+/*
+ * Read a single byte from the serial port. Returns 1 on success, 0
+ * otherwise. When the function is succesfull, the character read is
+ * written into its argument c.
+ */
+int serial_getc(void)
+{
+
+
+ while(!(*UART_RSR(EXC_UART00_BASE) & UART_RSR_RX_LEVEL_MSK));
+ return *UART_RD(EXC_UART00_BASE);
+}
+
+
+
+
+
+
--- /dev/null
+/*
+ * armboot - Startup Code for EPXA (Excalibur) devices
+ *
+ * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
+ * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
+ * Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
+ * Copyright (c) 2001 Alex Züpke <azu@sysgo.de>
+ * Copyright (C) 2002 Altera Corporation, San Jose, California, USA.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+
+#include "config.h"
+#include "version.h"
+
+#define INT_CTRL00_TYPE
+#define WATCHDOG00_TYPE
+
+#include "epxa/excalibur.h"
+#include "epxa/int_ctrl00.h"
+#include "epxa/watchdog00.h"
+
+/*
+ *************************************************************************
+ *
+ * Jump vector table as in table 3.1 in [1]
+ *
+ *************************************************************************
+ */
+
+
+.globl _start
+.globl ___altera_user_start
+
+ .section .init
+
+_start: b reset
+ ldr pc, _undefined_instruction
+ ldr pc, _software_interrupt
+ ldr pc, _prefetch_abort
+ ldr pc, _data_abort
+ ldr pc, _not_used
+ ldr pc, _irq
+ ldr pc, _fiq
+
+_undefined_instruction: .word undefined_instruction
+_software_interrupt: .word software_interrupt
+_prefetch_abort: .word prefetch_abort
+_data_abort: .word data_abort
+_not_used: .word not_used
+_irq: .word irq
+_fiq: .word fiq
+
+ .balignl 16,0xdeadbeef
+
+
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * do important init only if we don't start from memory!
+ * relocate armboot to ram
+ * setup stack
+ * jump to second stage
+ *
+ *************************************************************************
+ */
+
+/*
+ * the actual reset code
+ */
+
+reset:
+
+ /*
+ * we do sys-critical inits only at reboot,
+ * not when booting from ram!
+ */
+
+#ifdef CONFIG_INIT_CRITICAL
+ b ___altera_entry
+#else
+ b ___altera_user_start
+#endif
+
+/* Force the inclusion of the boot data in the image */
+
+ .word ___altera_user_entry
+
+ .text
+
+_TEXT_BASE:
+ .word TEXT_BASE
+
+.globl _armboot_start
+_armboot_start:
+ .word _start
+
+/*
+ * Note: armboot_end is defined by the (board-dependent) linker script
+ */
+.globl _armboot_end
+_armboot_end:
+ .word armboot_end
+
+/*
+ * _armboot_real_end is the first usable RAM address behind armboot
+ * and the various stacks
+ */
+.globl _armboot_real_end
+_armboot_real_end:
+ .word 0x0badc0de
+
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack memory (calculated at run-time) */
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+ .word 0x0badc0de
+
+/* IRQ stack memory (calculated at run-time) */
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+ .word 0x0badc0de
+#endif
+
+/*
+ * ___altera_user_start is the address in flash of the first line of code
+ * to be executed after the Altera boot code has configured the device.
+ * This is the line pointed to by user_start. Since this code is linked
+ * to start at zero, we need to correct for the offset of the flash within
+ * the memory map.
+ */
+ .set ___altera_user_start, user_start + EXC_EBI_BLOCK0_BASE
+
+user_start:
+
+ /*
+ * set the cpu to SVC32 mode
+ */
+
+ mrs r0,cpsr
+ bic r0,r0,#0x1f
+ orr r0,r0,#0x13
+ msr cpsr,r0
+
+ /*
+ * mask all IRQs
+ */
+ ldr r0, =INT_MC(EXC_INT_CTRL00_BASE)
+ mvn r1, #0
+ mov r1, r1, LSR #16
+ str r1, [r0]
+
+ /*
+ * disable MMU stuff and enable I-cache
+ */
+ mrc p15,0,r0,c1,c0
+ bic r0, r0, #0x00002000 @ clear bit 13 (X)
+ bic r0, r0, #0x0000000f @ clear bits 3-0 (WCAM)
+ orr r0, r0, #0x00001000 @ set bit 12 (I) Icache
+ orr r0, r0, #0x00000002 @ set bit 2 (A) Align
+ mcr p15,0,r0,c1,c0
+
+ /*
+ * flush v4 I/D caches
+ */
+ mov r0, #0
+ mcr p15, 0, r0, c7, c7, 0 // flush v3/v4 cache
+ mcr p15, 0, r0, c8, c7, 0 // flush v4 TLB
+
+relocate:
+ /*
+ * relocate armboot to RAM
+ */
+ ldr r0, _armboot_start /* r0 <- current position of code */
+ ldr r2, _armboot_end
+ ldr r1, _TEXT_BASE /* r1 <- destination address */
+
+ /* correct for the current execution address */
+
+ ldr r3, =EXC_EBI_BLOCK0_BASE
+ add r0, r0, r3
+ add r2, r2, r3
+
+ /*
+ * r0 = source address
+ * r1 = target address
+ * r2 = source end address
+ */
+copy_loop:
+ ldmia r0!, {r3-r10}
+ stmia r1!, {r3-r10}
+ cmp r0, r2
+ ble copy_loop
+
+ /* set up the stack */
+
+ ldr r0, _armboot_end
+ add r0, r0, #CONFIG_STACKSIZE
+ sub sp, r0, #12 /* leave 3 words for abort-stack */
+
+ ldr pc, _start_armboot
+
+_start_armboot: .word start_armboot
+
+/*
+ *************************************************************************
+ *
+ * Interrupt handling
+ *
+ *************************************************************************
+ */
+
+@
+@ IRQ stack frame.
+@
+#define S_FRAME_SIZE 72
+
+#define S_OLD_R0 68
+#define S_PSR 64
+#define S_PC 60
+#define S_LR 56
+#define S_SP 52
+
+#define S_IP 48
+#define S_FP 44
+#define S_R10 40
+#define S_R9 36
+#define S_R8 32
+#define S_R7 28
+#define S_R6 24
+#define S_R5 20
+#define S_R4 16
+#define S_R3 12
+#define S_R2 8
+#define S_R1 4
+#define S_R0 0
+
+#define MODE_SVC 0x13
+#define I_BIT 0x80
+
+/*
+ * use bad_save_user_regs for abort/prefetch/undef/swi ...
+ * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
+ */
+
+ .macro bad_save_user_regs
+ sub sp, sp, #S_FRAME_SIZE
+ stmia sp, {r0 - r12} @ Calling r0-r12
+ add r8, sp, #S_PC
+
+ ldr r2, _armboot_end
+ add r2, r2, #CONFIG_STACKSIZE
+ sub r2, r2, #8
+ ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
+ add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
+
+ add r5, sp, #S_SP
+ mov r1, lr
+ stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
+ mov r0, sp
+ .endm
+
+ .macro irq_save_user_regs
+ sub sp, sp, #S_FRAME_SIZE
+ stmia sp, {r0 - r12} @ Calling r0-r12
+ add r8, sp, #S_PC
+ stmdb r8, {sp, lr}^ @ Calling SP, LR
+ str lr, [r8, #0] @ Save calling PC
+ mrs r6, spsr
+ str r6, [r8, #4] @ Save CPSR
+ str r0, [r8, #8] @ Save OLD_R0
+ mov r0, sp
+ .endm
+
+ .macro irq_restore_user_regs
+ ldmia sp, {r0 - lr}^ @ Calling r0 - lr
+ mov r0, r0
+ ldr lr, [sp, #S_PC] @ Get PC
+ add sp, sp, #S_FRAME_SIZE
+ subs pc, lr, #4 @ return & move spsr_svc into cpsr
+ .endm
+
+ .macro get_bad_stack
+ ldr r13, _armboot_end @ setup our mode stack
+ add r13, r13, #CONFIG_STACKSIZE @ resides at top of normal stack
+ sub r13, r13, #8
+
+ str lr, [r13] @ save caller lr / spsr
+ mrs lr, spsr
+ str lr, [r13, #4]
+
+ mov r13, #MODE_SVC @ prepare SVC-Mode
+ msr spsr_c, r13
+ mov lr, pc
+ movs pc, lr
+ .endm
+
+ .macro get_irq_stack @ setup IRQ stack
+ ldr sp, IRQ_STACK_START
+ .endm
+
+ .macro get_fiq_stack @ setup FIQ stack
+ ldr sp, FIQ_STACK_START
+ .endm
+
+/*
+ * exception handlers
+ */
+ .align 5
+undefined_instruction:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_undefined_instruction
+
+ .align 5
+software_interrupt:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_software_interrupt
+
+ .align 5
+prefetch_abort:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_prefetch_abort
+
+ .align 5
+data_abort:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_data_abort
+
+ .align 5
+not_used:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_not_used
+
+#ifdef CONFIG_USE_IRQ
+
+ .align 5
+irq:
+ get_irq_stack
+ irq_save_user_regs
+ bl do_irq
+ irq_restore_user_regs
+
+ .align 5
+fiq:
+ get_fiq_stack
+ /* someone ought to write a more effiction fiq_save_user_regs */
+ irq_save_user_regs
+ bl do_fiq
+ irq_restore_user_regs
+
+#else
+
+ .align 5
+irq:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_irq
+
+ .align 5
+fiq:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_fiq
+
+#endif
+
+ .align 5
+.globl reset_cpu
+reset_cpu:
+ ldr r0,=WDOG_RELOAD(EXC_WATCHDOG00_BASE)
+ mov r1,#0x10
+ str r1,[r0]
+ /* wait for reset */
+1:
+ b 1b
static const char version[] =
"smc91111.c:v1.0 04/25/01 by Daris A Nevil (dnevil@snmc.com)\n";
-
#define SMC_DEBUG 0
-
/*------------------------------------------------------------------------
.
. Configuration options, for the experienced user to change.
// Memory sizing constant
#define LAN91C111_MEMORY_MULTIPLIER (1024*2)
-#define SMC_BASE_ADDRESS 0x20000300
+#ifndef SMC_BASE_ADDRESS
+#define SMC_BASE_ADDRESS 0x20000300
+#endif
+
#define SMC_DEV_NAME "SMC91111"
#define SMC_PHY_ADDR 0x0000
#define SMC_ALLOC_MAX_TRY 5
------------------------------------------------------------
*/
-/** This is hardcoded for now.
- * Once the flash works correctly the mac addr. can be
- * fetched from FLASHBLOCK 1 / OFFSET 0x10 using
- * smc_get_macaddr( smc_mac_addr );
+static char smc_mac_addr[] = {0x02, 0x80, 0xad, 0x20, 0x31, 0xb8};
+
+/*
+ * This function must be called before smc_open() if you want to override
+ * the default mac address.
*/
-byte smc_mac_addr[6] = {0x02, 0x80, 0xad, 0x20, 0x31, 0xb8};
+void smc_set_mac_addr(const char *addr) {
+ int i;
+
+ for (i=0; i < sizeof(smc_mac_addr); i++){
+ smc_mac_addr[i] = addr[i];
+ }
+}
+
+/*
+ * smc_get_macaddr is no longer used. If you want to override the default
+ * mac address, call smc_get_mac_addr as a part of the board initialisation.
+ */
+
+#if 0
void smc_get_macaddr( byte *addr ) {
/* MAC ADDRESS AT FLASHBLOCK 1 / OFFSET 0x10 */
unsigned char *dnp1110_mac = (unsigned char *) (0xE8000000 + 0x20010);
addr[5] = *(dnp1110_mac+5);
}
}
+#endif
/***********************************************
* Show available memory *
// SMC_SELECT_BANK(0);
// SMC_outw(0, RPC_REG);
- /*
- According to Becker, I have to set the hardware address
- at this point, because the (l)user can set it with an
- ioctl. Easily done...
- */
SMC_SELECT_BANK( 1 );
+
for ( i = 0; i < 6; i ++ )
SMC_outb( smc_mac_addr[i], ADDR0_REG + i );
.-------------------------------------------------------------*/
static void smc_wait_ms(unsigned int ms)
{
- udelay(ms*100000);
+ udelay(ms*1000);
}
#include "types.h"
#include "config.h"
+/*
+ * This function may be called by the board specific initialisation code
+ * in order to override the default mac address.
+ */
+
+void smc_set_mac_addr(const char *addr);
/* I want some simple types */
--- /dev/null
+/*
+ * Copyright (c) 2000-2002 Altera Corporation, San Jose, California, USA.
+ * All rights reserved.
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * Configuation settings for the EPXA1 Development Board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "epxa/excalibur.h"
+
+/*
+ * If we are developing, we might want to start armboot from ram
+ * so we MUST NOT initialize critical regs like mem-timing ...
+ * However at the moment, we're booting from flash.
+ */
+
+#define CONFIG_INIT_CRITICAL /* undef for developing */
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM922 1 /* This is an ARM922 CPU */
+#define CONFIG_EPXA1DB 1 /* epxa1 developemnt board */
+
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_MALLOC_SIZE (CFG_ENV_SIZE + 128*1024)
+
+#define CONFIG_NO_IDE
+#define CONFIG_NO_PCMCIA
+
+/*
+ * Hardware drivers
+ */
+
+#define CONFIG_DRIVER_SMC91111
+#define SMC_BASE_ADDRESS (EXC_EBI_BLOCK3_BASE + 0x300)
+#define CONFIG_EPXA1DB_MAC_ADDR
+
+/*
+ * select serial console configuration
+ */
+
+/* allow to overwrite serial and ethaddr */
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE 57600
+
+#define CONFIG_COMMANDS CONFIG_CMD_DFL
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTARGS "root=/dev/nfs mem=16M console=ttyUA0,57600 nfsroot=/usr/devel/flashdisk_top/%s,rsize=4096,wsize=4096 ip=137.57.134.44:137.57.134.41:137.57.134.254:255.255.255.0:epxa1db-1:eth0:off"
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 137.57.134.44
+#define CONFIG_SERVERIP 137.57.134.151
+#define CONFIG_BOOTFILE "vmlinux.exe"
+#define CONFIG_BOOTCOMMAND "tftp;bootm"
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "epxa1db # " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x00600000 /* 4 ... 6 MB in DRAM */
+
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR 0xA00000 /* default load address */
+
+#define CFG_HZ EXC_AHB2_CLK_FREQUENCY
+ /* valid baudrates */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_DOS_PARTITION 0 /* DOS partitiion support */
+
+#ifndef __ASSEMBLY__
+/*-----------------------------------------------------------------------
+ * Board specific extension for bd_info
+ *
+ * This structure is embedded in the global bd_info (bd_t) structure
+ * and can be used by the board specific code (eg board/...)
+ */
+
+struct bd_info_ext
+{
+ /* helper variable for board environment handling
+ *
+ * env_crc_valid == 0 => uninitialised
+ * env_crc_valid > 0 => environment crc in flash is valid
+ * env_crc_valid < 0 => environment crc in flash is invalid
+ */
+ int env_crc_valid;
+};
+#endif
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+
+#define CONFIG_NR_DRAM_BANKS 1
+
+#define PHYS_FLASH_1 EXC_EBI_BLOCK0_BASE /* Flash Bank #1 */
+#define PHYS_FLASH_2 EXC_EBI_BLOCK1_BASE /* FLASH Bank #2 */
+
+#define CFG_FLASH_BASE PHYS_FLASH_1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT (63+8) /* max number of sectors on one chip */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT (2*EXC_AHB2_CLK_FREQUENCY) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT (2*EXC_AHB2_CLK_FREQUENCY) /* Timeout for Flash Write */
+
+/*
+ * we put the env storage below offset 0x180000 so as to leave space for the linux flash
+ * file system.
+ */
+
+#define CFG_ENV_SIZE 0x10000
+#define CFG_ENV_ADDR (EXC_EBI_BLOCK0_BASE + 0x40000 - CFG_ENV_SIZE) /* Addr of
+Environment Sector */
+
+#endif /* __CONFIG_H */
+
+
+
+
--- /dev/null
+#ifndef __CLOCK_CTRL00_H
+#define __CLOCK_CTRL00_H
+
+/*
+ * Register definitions for the Clock Control Logic
+ */
+
+/*
+ * Copyright (c) 2000-2002 Altera Corporation, San Jose, California, USA.
+ * All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * This agreement shall be governed in all respects by the laws of the State
+ * of California and by the laws of the United States of America.
+ */
+
+#define CLK_PLL1_NCNT(base_addr) (CLOCK_CTRL00_TYPE (base_addr ))
+#define CLK_PLL1_NCNT_LSB_MSK (0x7)
+#define CLK_PLL1_NCNT_LSB_OFST (0)
+#define CLK_PLL1_NCNT_MSB_MSK (0xF00)
+#define CLK_PLL1_NCNT_MSB_OFST (8)
+#define CLK_PLL1_NCNT_CT_MSK (0x70000)
+#define CLK_PLL1_NCNT_CT_OFST (16)
+
+#define CLK_PLL1_MCNT(base_addr) (CLOCK_CTRL00_TYPE (base_addr + 0x4 ))
+#define CLK_PLL1_MCNT_LSB_MSK (0x7)
+#define CLK_PLL1_MCNT_LSB_OFST (0)
+#define CLK_PLL1_MCNT_MSB_MSK (0xF00)
+#define CLK_PLL1_MCNT_MSB_OFST (8)
+#define CLK_PLL1_MCNT_CT_MSK (0x70000)
+#define CLK_PLL1_MCNT_CT_OFST (16)
+
+#define CLK_PLL1_KCNT(base_addr) (CLOCK_CTRL00_TYPE (base_addr + 0x8 ))
+#define CLK_PLL1_KCNT_LSB_MSK (0x7)
+#define CLK_PLL1_KCNT_LSB_OFST (0)
+#define CLK_PLL1_KCNT_MSB_MSK (0xF00)
+#define CLK_PLL1_KCNT_MSB_OFST (8)
+#define CLK_PLL1_KCNT_CT_MSK (0x70000)
+#define CLK_PLL1_KCNT_CT_OFST (16)
+
+#define CLK_PLL1_CTRL(base_addr) (CLOCK_CTRL00_TYPE (base_addr + 0xC ))
+#define CLK_PLL1_CTRL_P_MSK (0x1)
+#define CLK_PLL1_CTRL_P_OFST (0)
+#define CLK_PLL1_CTRL_CTRL_MSK (0x7FFE)
+#define CLK_PLL1_CTRL_CTRL_OFST (1)
+
+#define CLK_PLL2_NCNT(base_addr) (CLOCK_CTRL00_TYPE (base_addr + 0x10 ))
+#define CLK_PLL2_NCNT_LSB_MSK (0x7)
+#define CLK_PLL2_NCNT_LSB_OFST (0)
+#define CLK_PLL2_NCNT_MSB_MSK (0xF00)
+#define CLK_PLL2_NCNT_MSB_OFST (8)
+#define CLK_PLL2_NCNT_CT_MSK (0x70000)
+#define CLK_PLL2_NCNT_CT_OFST (16)
+
+#define CLK_PLL2_MCNT(base_addr) (CLOCK_CTRL00_TYPE (base_addr + 0x14 ))
+#define CLK_PLL2_MCNT_LSB_MSK (0x7)
+#define CLK_PLL2_MCNT_LSB_OFST (0)
+#define CLK_PLL2_MCNT_MSB_MSK (0xF00)
+#define CLK_PLL2_MCNT_MSB_OFST (8)
+#define CLK_PLL2_MCNT_CT_MSK (0x70000)
+#define CLK_PLL2_MCNT_CT_OFST (16)
+
+#define CLK_PLL2_KCNT(base_addr) (CLOCK_CTRL00_TYPE (base_addr + 0x18 ))
+#define CLK_PLL2_KCNT_LSB_MSK (0x7)
+#define CLK_PLL2_KCNT_LSB_OFST (0)
+#define CLK_PLL2_KCNT_MSB_MSK (0xF00)
+#define CLK_PLL2_KCNT_MSB_OFST (8)
+#define CLK_PLL2_KCNT_CT_MSK (0x70000)
+#define CLK_PLL2_KCNT_CT_OFST (16)
+
+#define CLK_PLL2_CTRL(base_addr) (CLOCK_CTRL00_TYPE (base_addr + 0x1C ))
+#define CLK_PLL2_CTRL_P_MSK (0x1)
+#define CLK_PLL2_CTRL_P_OFST (0)
+#define CLK_PLL2_CTRL_CTRL_MSK (0x7FFE)
+#define CLK_PLL2_CTRL_CTRL_OFST (0)
+
+#define CLK_DERIVE(base_addr) (CLOCK_CTRL00_TYPE (base_addr + 0x20 ))
+#define CLK_DERIVE_DF2_MSK (0x30)
+#define CLK_DERIVE_DF2_OFST (4)
+#define CLK_DERIVE_BP1_MSK (0x1000)
+#define CLK_DERIVE_BP1_OFST (12)
+#define CLK_DERIVE_BP2_MSK (0x2000)
+#define CLK_DERIVE_BP2_OFST (13)
+
+#define CLK_STATUS(base_addr) (CLOCK_CTRL00_TYPE (base_addr + 0x24 ))
+#define CLK_STATUS_L1_MSK (0x1)
+#define CLK_STATUS_L1_OFST (0)
+#define CLK_STATUS_L2_MSK (0x2)
+#define CLK_STATUS_L2_OFST (1)
+#define CLK_STATUS_C1_MSK (0x4)
+#define CLK_STATUS_C1_OFST (2)
+#define CLK_STATUS_C2_MSK (0x8)
+#define CLK_STATUS_C2_OFST (3)
+#define CLK_STATUS_P1_MSK (0x10)
+#define CLK_STATUS_P1_OFST (4)
+#define CLK_STATUS_P2_MSK (0x20)
+#define CLK_STATUS_P2_OFST (5)
+
+#define CLK_AHB1_COUNT(base_addr) (CLOCK_CTRL00_TYPE (base_addr + 0x28 ))
+#define CLK_AHB1_COUNT_MSK (0xFFFFFFFF)
+#define CLK_AHB1_COUNT_OFST (0)
+
+#endif /* __CLOCK_CTRL00_H */
--- /dev/null
+#ifndef __EBI00_H\r
+#define __EBI00_H\r
+\r
+/*\r
+ * Register definitions for the ExternalBus Interface\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2000-2002 Altera Corporation, San Jose, California, USA. \r
+ * All rights reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy\r
+ * of this software and associated documentation files (the "Software"), to \r
+ * deal in the Software without restriction, including without limitation the \r
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r
+ * sell copies of the Software, and to permit persons to whom the Software is \r
+ * furnished to do so, subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in \r
+ * all copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR \r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, \r
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\r
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER \r
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING \r
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER \r
+ * DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * This agreement shall be governed in all respects by the laws of the State \r
+ * of California and by the laws of the United States of America.\r
+ */\r
+ \r
+#define EBI_CR(base_addr) (EBI00_TYPE (base_addr + 0x00 ))\r
+#define EBI_CR_BP_MSK (0x1)\r
+#define EBI_CR_BP_OFST (0)\r
+#define EBI_CR_OP_MSK (0x2)\r
+#define EBI_CR_OP_OFST (1)\r
+#define EBI_CR_WP_MSK (0x4)\r
+#define EBI_CR_WP_OFST (2)\r
+#define EBI_CR_EO_MSK (0x8)\r
+#define EBI_CR_EO_OFST (3)\r
+#define EBI_CR_SP_MSK (0x10)\r
+#define EBI_CR_SP_OFST (4)\r
+#define EBI_CR_CLK_DIV_MSK (0x3C0)\r
+#define EBI_CR_CLK_DIV_OFST (6)\r
+#define EBI_CR_TIMEOUT_MSK (0x3FC00)\r
+#define EBI_CR_TIMEOUT_OFST (10)\r
+#define EBI_CR_TE_MSK (0x40000)\r
+#define EBI_CR_TE_OFST (18)\r
+#define EBI_CR_CE_MSK (0x80000)\r
+#define EBI_CR_CE_OFST (19)\r
+#define EBI_CR_R_MSK (0x80000000)\r
+#define EBI_CR_R_OFST (31)\r
+\r
+#define EBI_SR(base_addr) (EBI00_TYPE (base_addr + 0x00 ))\r
+#define EBI_SR_BP_MSK (0x1)\r
+#define EBI_SR_BP_OFST (0)\r
+#define EBI_SR_OP_MSK (0x2)\r
+#define EBI_SR_OP_OFST (1)\r
+#define EBI_SR_WP_MSK (0x4)\r
+#define EBI_SR_WP_OFST (2)\r
+#define EBI_SR_EO_MSK (0x8)\r
+#define EBI_SR_EO_OFST (3)\r
+#define EBI_SR_SP_MSK (0x10)\r
+#define EBI_SR_SP_OFST (4)\r
+#define EBI_SR_CLK_DIV_MSK (0x3C0)\r
+#define EBI_SR_CLK_DIV_OFST (6)\r
+#define EBI_SR_TIMEOUT_MSK (0x3FC00)\r
+#define EBI_SR_TIMEOUT_OFST (10)\r
+#define EBI_SR_TE_MSK (0x40000)\r
+#define EBI_SR_TE_OFST (18)\r
+#define EBI_SR_CE_MSK (0x80000)\r
+#define EBI_SR_CE_OFST (19)\r
+#define EBI_SR_RE_MSK (0x8000000)\r
+#define EBI_SR_RE_OFST (27)\r
+#define EBI_SR_RF_MSK (0x10000000)\r
+#define EBI_SR_RF_OFST (28)\r
+#define EBI_SR_XE_MSK (0x20000000)\r
+#define EBI_SR_XE_OFST (29)\r
+#define EBI_SR_XF_MSK (0x40000000)\r
+#define EBI_SR_XF_OFST (30)\r
+#define EBI_SR_XP_MSK (0x80000000)\r
+#define EBI_SR_XP_OFST (31)\r
+\r
+#define EBI_BLOCK0(base_addr) (EBI00_TYPE (base_addr + 0x10 ))\r
+#define EBI_BLOCK0_SA_MSK 0x1\r
+#define EBI_BLOCK0_SA_OFST (0)\r
+#define EBI_BLOCK0_WAIT_MSK (0x1E)\r
+#define EBI_BLOCK0_WAIT_OFST (1)\r
+#define EBI_BLOCK0_CP_MSK 0x20\r
+#define EBI_BLOCK0_CP_OFST (5)\r
+#define EBI_BLOCK0_BH_MSK 0x40\r
+#define EBI_BLOCK0_BH_OFST (6)\r
+#define EBI_BLOCK0_BE_MSK 0x80\r
+#define EBI_BLOCK0_BE_OFST (7)\r
+\r
+#define EBI_BLOCK1(base_addr) (EBI00_TYPE (base_addr + 0x14 ))\r
+#define EBI_BLOCK1_SA_MSK 0x1\r
+#define EBI_BLOCK1_SA_OFST (0)\r
+#define EBI_BLOCK1_WAIT_MSK (0x1E)\r
+#define EBI_BLOCK1_WAIT_OFST (1)\r
+#define EBI_BLOCK1_CP_MSK 0x20\r
+#define EBI_BLOCK1_CP_OFST (5)\r
+#define EBI_BLOCK1_BH_MSK 0x40\r
+#define EBI_BLOCK1_BH_OFST (6)\r
+#define EBI_BLOCK1_BE_MSK 0x80\r
+#define EBI_BLOCK1_BE_OFST (7)\r
+\r
+#define EBI_BLOCK2(base_addr) (EBI00_TYPE (base_addr + 0x18 ))\r
+#define EBI_BLOCK2_SA_MSK 0x1\r
+#define EBI_BLOCK2_SA_OFST (0)\r
+#define EBI_BLOCK2_WAIT_MSK (0x1E)\r
+#define EBI_BLOCK2_WAIT_OFST (1)\r
+#define EBI_BLOCK2_CP_MSK 0x20\r
+#define EBI_BLOCK2_CP_OFST (5)\r
+#define EBI_BLOCK2_BH_MSK 0x40\r
+#define EBI_BLOCK2_BH_OFST (6)\r
+#define EBI_BLOCK2_BE_MSK 0x80\r
+#define EBI_BLOCK2_BE_OFST (7)\r
+\r
+#define EBI_BLOCK3(base_addr) (EBI00_TYPE (base_addr + 0x1C ))\r
+#define EBI_BLOCK3_SA_MSK 0x1\r
+#define EBI_BLOCK3_SA_OFST (0)\r
+#define EBI_BLOCK3_WAIT_MSK (0x1E)\r
+#define EBI_BLOCK3_WAIT_OFST (1)\r
+#define EBI_BLOCK3_CP_MSK 0x20\r
+#define EBI_BLOCK3_CP_OFST (5)\r
+#define EBI_BLOCK3_BH_MSK 0x40\r
+#define EBI_BLOCK3_BH_OFST (6)\r
+#define EBI_BLOCK3_BE_MSK 0x80\r
+#define EBI_BLOCK3_BE_OFST (7)\r
+\r
+#define EBI_INT_SR(base_addr) (EBI00_TYPE (base_addr + 0x20 ))\r
+#define EBI_INT_SR_TOI (0x1)\r
+#define EBI_INT_SR_OFST (0)\r
+\r
+#define EBI_INT_ADDRSR(base_addr) (EBI00_TYPE (base_addr + 0x24 ))\r
+#define EBI_INT_ADDRESS_MSK (0xFFFFFF)\r
+#define EBI_INT_ADDRESS_OFST (0)\r
+#define EBI_INT_B0_MSK (0x10000000)\r
+#define EBI_INT_B0_OFST (28)\r
+#define EBI_INT_B1_MSK (0x20000000)\r
+#define EBI_INT_B1_OFST (29)\r
+#define EBI_INT_B2_MSK (0x40000000)\r
+#define EBI_INT_B2_OFST (30)\r
+#define EBI_INT_B3_MSK (0x80000000)\r
+#define EBI_INT_B3_OFST (31)\r
+\r
+#endif /* __EBI00_H */\r
--- /dev/null
+/*
+ *
+ * This file contains the register definitions for the Excalibur
+ * Interrupt controller INT_CTRL00.
+ */
+
+/*
+ * Copyright (c) 2000-2002 Altera Corporation, San Jose, California, USA.
+ * All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * This agreement shall be governed in all respects by the laws of the State
+ * of California and by the laws of the United States of America.
+ */
+
+#ifndef __INT_CTRL00_H
+#define __INT_CTRL00_H
+
+#define INT_MS(base_addr) (INT_CTRL00_TYPE (base_addr + 0x00 ))
+#define INT_MS_FC_MSK (0x10000)
+#define INT_MS_FC_OFST (16)
+#define INT_MS_CR_MSK (0x8000)
+#define INT_MS_CR_OFST (15)
+#define INT_MS_CT_MSK (0x4000)
+#define INT_MS_CT_OFST (14)
+#define INT_MS_AE_MSK (0x2000)
+#define INT_MS_AE_OFST (13)
+#define INT_MS_PE_MSK (0x1000)
+#define INT_MS_PE_OFST (12)
+#define INT_MS_EE_MSK (0x0800)
+#define INT_MS_EE_OFST (11)
+#define INT_MS_PS_MSK (0x0400)
+#define INT_MS_PS_OFST (10)
+#define INT_MS_T1_MSK (0x0200)
+#define INT_MS_T1_OFST (9)
+#define INT_MS_T0_MSK (0x0100)
+#define INT_MS_T0_OFST (8)
+#define INT_MS_UA_MSK (0x0080)
+#define INT_MS_UA_OFST (7)
+#define INT_MS_IP_MSK (0x0040)
+#define INT_MS_IP_OFST (6)
+#define INT_MS_P5_MSK (0x0020)
+#define INT_MS_P5_OFST (5)
+#define INT_MS_P4_MSK (0x0010)
+#define INT_MS_P4_OFST (4)
+#define INT_MS_P3_MSK (0x0008)
+#define INT_MS_P3_OFST (3)
+#define INT_MS_P2_MSK (0x0004)
+#define INT_MS_P2_OFST (2)
+#define INT_MS_P1_MSK (0x0002)
+#define INT_MS_P1_OFST (1)
+#define INT_MS_P0_MSK (0x0001)
+#define INT_MS_P0_OFST (0)
+
+#define INT_MC(base_addr) (INT_CTRL00_TYPE (base_addr + 0x04 ))
+#define INT_MC_FC_MSK (0x10000)
+#define INT_MC_FC_OFST (16)
+#define INT_MC_CR_MSK (0x8000)
+#define INT_MC_CR_OFST (15)
+#define INT_MC_CT_MSK (0x4000)
+#define INT_MC_CT_OFST (14)
+#define INT_MC_AE_MSK (0x2000)
+#define INT_MC_AE_OFST (13)
+#define INT_MC_PE_MSK (0x1000)
+#define INT_MC_PE_OFST (12)
+#define INT_MC_EE_MSK (0x0800)
+#define INT_MC_EE_OFST (11)
+#define INT_MC_PS_MSK (0x0400)
+#define INT_MC_PS_OFST (10)
+#define INT_MC_T1_MSK (0x0200)
+#define INT_MC_T1_OFST (9)
+#define INT_MC_T0_MSK (0x0100)
+#define INT_MC_T0_OFST (8)
+#define INT_MC_UA_MSK (0x0080)
+#define INT_MC_UA_OFST (7)
+#define INT_MC_IP_MSK (0x0040)
+#define INT_MC_IP_OFST (6)
+#define INT_MC_P5_MSK (0x0020)
+#define INT_MC_P5_OFST (5)
+#define INT_MC_P4_MSK (0x0010)
+#define INT_MC_P4_OFST (4)
+#define INT_MC_P3_MSK (0x0008)
+#define INT_MC_P3_OFST (3)
+#define INT_MC_P2_MSK (0x0004)
+#define INT_MC_P2_OFST (2)
+#define INT_MC_P1_MSK (0x0002)
+#define INT_MC_P1_OFST (1)
+#define INT_MC_P0_MSK (0x0001)
+#define INT_MC_P0_OFST (0)
+
+#define INT_SS(base_addr) (INT_CTRL00_TYPE (base_addr + 0x08 ))
+#define INT_SS_FC_MSK (0x8000)
+#define INT_SS_FC_OFST (15)
+#define INT_SS_CR_MSK (0x8000)
+#define INT_SS_CR_OFST (15)
+#define INT_SS_CT_MSK (0x4000)
+#define INT_SS_CT_OFST (14)
+#define INT_SS_AE_MSK (0x2000)
+#define INT_SS_AE_OFST (13)
+#define INT_SS_PE_MSK (0x1000)
+#define INT_SS_PE_OFST (12)
+#define INT_SS_EE_MSK (0x0800)
+#define INT_SS_EE_OFST (11)
+#define INT_SS_PS_MSK (0x0400)
+#define INT_SS_PS_OFST (10)
+#define INT_SS_T1_MSK (0x0200)
+#define INT_SS_T1_OFST (9)
+#define INT_SS_T0_MSK (0x0100)
+#define INT_SS_T0_OFST (8)
+#define INT_SS_UA_MSK (0x0080)
+#define INT_SS_UA_OFST (7)
+#define INT_SS_IP_MSK (0x0040)
+#define INT_SS_IP_OFST (6)
+#define INT_SS_P5_MSK (0x0020)
+#define INT_SS_P5_OFST (5)
+#define INT_SS_P4_MSK (0x0010)
+#define INT_SS_P4_OFST (4)
+#define INT_SS_P3_MSK (0x0008)
+#define INT_SS_P3_OFST (3)
+#define INT_SS_P2_MSK (0x0004)
+#define INT_SS_P2_OFST (2)
+#define INT_SS_P1_MSK (0x0002)
+#define INT_SS_P1_OFST (1)
+#define INT_SS_P0_MSK (0x0001)
+#define INT_SS_P0_OFST (0)
+
+#define INT_RS(base_addr) (INT_CTRL00_TYPE (base_addr + 0x0C ))
+#define INT_RS_FC_MSK (0x10000)
+#define INT_RS_FC_OFST (16)
+#define INT_RS_CR_MSK (0x8000)
+#define INT_RS_CR_OFST (15)
+#define INT_RS_CT_MSK (0x4000)
+#define INT_RS_CT_OFST (14)
+#define INT_RS_AE_MSK (0x2000)
+#define INT_RS_AE_OFST (13)
+#define INT_RS_PE_MSK (0x1000)
+#define INT_RS_PE_OFST (12)
+#define INT_RS_EE_MSK (0x0800)
+#define INT_RS_EE_OFST (11)
+#define INT_RS_PS_MSK (0x0400)
+#define INT_RS_PS_OFST (10)
+#define INT_RS_T1_MSK (0x0200)
+#define INT_RS_T1_OFST (9)
+#define INT_RS_T0_MSK (0x0100)
+#define INT_RS_T0_OFST (8)
+#define INT_RS_UA_MSK (0x0080)
+#define INT_RS_UA_OFST (7)
+#define INT_RS_IP_MSK (0x0040)
+#define INT_RS_IP_OFST (6)
+#define INT_RS_P5_MSK (0x0020)
+#define INT_RS_P5_OFST (5)
+#define INT_RS_P4_MSK (0x0010)
+#define INT_RS_P4_OFST (4)
+#define INT_RS_P3_MSK (0x0008)
+#define INT_RS_P3_OFST (3)
+#define INT_RS_P2_MSK (0x0004)
+#define INT_RS_P2_OFST (2)
+#define INT_RS_P1_MSK (0x0002)
+#define INT_RS_P1_OFST (1)
+#define INT_RS_P0_MSK (0x0001)
+#define INT_RS_P0_OFST (0)
+
+#define INT_ID(base_addr) (INT_CTRL00_TYPE (base_addr + 0x10 ))
+#define INT_ID_ID_MSK (0x3F)
+#define INT_ID_ID_OFST (0)
+
+#define INT_PLD_PRIORITY(base_addr) (INT_CTRL00_TYPE (base_addr + 0x14 ))
+#define INT_PLD_PRIORITY_PRI_MSK (0x3F)
+#define INT_PLD_PRIORITY_PRI_OFST (0)
+#define INT_PLD_PRIORITY_GA_MSK (0x40)
+#define INT_PLD_PRIORITY_GA_OFST (6)
+
+#define INT_PLD_MODE(base_addr) (INT_CTRL00_TYPE (base_addr + 0x18 ))
+#define INT_PLD_MODE_MODE_MSK (0x3)
+#define INT_PLD_MODE_MODE_OFST (0)
+
+#define INT_PRIORITY_P0(base_addr) (INT_CTRL00_TYPE (base_addr + 0x80 ))
+#define INT_PRIORITY_P0_PRI_MSK (0x3F)
+#define INT_PRIORITY_P0_PRI_OFST (0)
+#define INT_PRIORITY_P0_FQ_MSK (0x40)
+#define INT_PRIORITY_P0_FQ_OFST (6)
+
+#define INT_PRIORITY_P1(base_addr) (INT_CTRL00_TYPE (base_addr + 0x84 ))
+#define INT_PRIORITY_P1_PRI_MSK (0x3F)
+#define INT_PRIORITY_P1_PRI_OFST (0)
+#define INT_PRIORITY_P1_FQ_MSK (0x40)
+#define INT_PRIORITY_P1_FQ_OFST (6)
+
+#define INT_PRIORITY_P2(base_addr) (INT_CTRL00_TYPE (base_addr + 0x88 ))
+#define INT_PRIORITY_P2_PRI_MSK (0x3F)
+#define INT_PRIORITY_P2_PRI_OFST (0)
+#define INT_PRIORITY_P2_FQ_MSK (0x40)
+#define INT_PRIORITY_P2_FQ_OFST (6)
+
+#define INT_PRIORITY_P3(base_addr) (INT_CTRL00_TYPE (base_addr + 0x8C ))
+#define INT_PRIORITY_P3_PRI_MSK (0x3F)
+#define INT_PRIORITY_P3_PRI_OFST (0)
+#define INT_PRIORITY_P3_FQ_MSK (0x40)
+#define INT_PRIORITY_P3_FQ_OFST (6)
+
+#define INT_PRIORITY_P4(base_addr) (INT_CTRL00_TYPE (base_addr + 0x90 ))
+#define INT_PRIORITY_P4_PRI_MSK (0x3F)
+#define INT_PRIORITY_P4_PRI_OFST (0)
+#define INT_PRIORITY_P4_FQ_MSK (0x40)
+#define INT_PRIORITY_P4_FQ_OFST (6)
+
+#define INT_PRIORITY_P5(base_addr) (INT_CTRL00_TYPE (base_addr + 0x94 ))
+#define INT_PRIORITY_P5_PRI_MSK (0x3F)
+#define INT_PRIORITY_P5_PRI_OFST (0)
+#define INT_PRIORITY_P5_FQ_MSK (0x40)
+#define INT_PRIORITY_P5_FQ_OFST (6)
+
+#define INT_PRIORITY_IP(base_addr) (INT_CTRL00_TYPE (base_addr + 0x98 ))
+#define INT_PRIORITY_IP_PRI_MSK (0x3F)
+#define INT_PRIORITY_IP_PRI_OFST (0)
+#define INT_PRIORITY_IP_FQ_MSK (0x40)
+#define INT_PRIORITY_IP_FQ_OFST (6)
+
+#define INT_PRIORITY_UA(base_addr) (INT_CTRL00_TYPE (base_addr + 0x9C ))
+#define INT_PRIORITY_UA_PRI_MSK (0x3F)
+#define INT_PRIORITY_UA_PRI_OFST (0)
+#define INT_PRIORITY_UA_FQ_MSK (0x40)
+#define INT_PRIORITY_UA_FQ_OFST (6)
+
+#define INT_PRIORITY_T0(base_addr) (INT_CTRL00_TYPE (base_addr + 0xA0 ))
+#define INT_PRIORITY_T0_PRI_MSK (0x3F)
+#define INT_PRIORITY_T0_PRI_OFST (0)
+#define INT_PRIORITY_T0_FQ_MSK (0x40)
+#define INT_PRIORITY_T0_FQ_OFST (6)
+
+#define INT_PRIORITY_T1(base_addr) (INT_CTRL00_TYPE (base_addr + 0xA4 ))
+#define INT_PRIORITY_T1_PRI_MSK (0x3F)
+#define INT_PRIORITY_T1_PRI_OFST (0)
+#define INT_PRIORITY_T1_FQ_MSK (0x40)
+#define INT_PRIORITY_T1_FQ_OFST (6)
+
+#define INT_PRIORITY_PS(base_addr) (INT_CTRL00_TYPE (base_addr + 0xA8 ))
+#define INT_PRIORITY_PS_PRI_MSK (0x3F)
+#define INT_PRIORITY_PS_PRI_OFST (0)
+#define INT_PRIORITY_PS_FQ_MSK (0x40)
+#define INT_PRIORITY_PS_FQ_OFST (6)
+
+#define INT_PRIORITY_EE(base_addr) (INT_CTRL00_TYPE (base_addr + 0xAC ))
+#define INT_PRIORITY_EE_PRI_MSK (0x3F)
+#define INT_PRIORITY_EE_PRI_OFST (0)
+#define INT_PRIORITY_EE_FQ_MSK (0x40)
+#define INT_PRIORITY_EE_FQ_OFST (6)
+
+#define INT_PRIORITY_PE(base_addr) (INT_CTRL00_TYPE (base_addr + 0xB0 ))
+#define INT_PRIORITY_PE_PRI_MSK (0x3F)
+#define INT_PRIORITY_PE_PRI_OFST (0)
+#define INT_PRIORITY_PE_FQ_MSK (0x40)
+#define INT_PRIORITY_PE_FQ_OFST (6)
+
+#define INT_PRIORITY_AE(base_addr) (INT_CTRL00_TYPE (base_addr + 0xB4 ))
+#define INT_PRIORITY_AE_PRI_MSK (0x3F)
+#define INT_PRIORITY_AE_PRI_OFST (0)
+#define INT_PRIORITY_AE_FQ_MSK (0x40)
+#define INT_PRIORITY_AE_FQ_OFST (6)
+
+#define INT_PRIORITY_CT(base_addr) (INT_CTRL00_TYPE (base_addr + 0xB8 ))
+#define INT_PRIORITY_CT_PRI_MSK (0x3F)
+#define INT_PRIORITY_CT_PRI_OFST (0)
+#define INT_PRIORITY_CT_FQ_MSK (0x40)
+#define INT_PRIORITY_CT_FQ_OFST (6)
+
+#define INT_PRIORITY_CR(base_addr) (INT_CTRL00_TYPE (base_addr + 0xBC ))
+#define INT_PRIORITY_CR_PRI_MSK (0x3F)
+#define INT_PRIORITY_CR_PRI_OFST (0)
+#define INT_PRIORITY_CR_FQ_MSK (0x40)
+#define INT_PRIORITY_CR_FQ_OFST (6)
+
+#define INT_PRIORITY_FC(base_addr) (INT_CTRL00_TYPE (base_addr + 0xC0 ))
+#define INT_PRIORITY_FC_PRI_MSK (0x3F)
+#define INT_PRIORITY_FC_PRI_OFST (0)
+#define INT_PRIORITY_FC_FQ_MSK (0x40)
+#define INT_PRIORITY_FC_FQ_OFST (6)
+#define INT_PRIORITY_IP(base_addr) (INT_CTRL00_TYPE (base_addr + 0x98 ))
+#define INT_PRIORITY_IP_PRI_MSK (0x3F)
+#define INT_PRIORITY_IP_PRI_OFST (0)
+#define INT_PRIORITY_IP_FQ_MSK (0x40)
+#define INT_PRIORITY_IP_FQ_OFST (6)
+
+#define INT_PRIORITY_UA(base_addr) (INT_CTRL00_TYPE (base_addr + 0x9C ))
+#define INT_PRIORITY_UA_PRI_MSK (0x3F)
+#define INT_PRIORITY_UA_PRI_OFST (0)
+#define INT_PRIORITY_UA_FQ_MSK (0x40)
+#define INT_PRIORITY_UA_FQ_OFST (6)
+
+#define INT_PRIORITY_T0(base_addr) (INT_CTRL00_TYPE (base_addr + 0xA0 ))
+#define INT_PRIORITY_T0_PRI_MSK (0x3F)
+#define INT_PRIORITY_T0_PRI_OFST (0)
+#define INT_PRIORITY_T0_FQ_MSK (0x40)
+#define INT_PRIORITY_T0_FQ_OFST (6)
+
+#define INT_PRIORITY_T1(base_addr) (INT_CTRL00_TYPE (base_addr + 0xA4 ))
+#define INT_PRIORITY_T1_PRI_MSK (0x3F)
+#define INT_PRIORITY_T1_PRI_OFST (0)
+#define INT_PRIORITY_T1_FQ_MSK (0x40)
+#define INT_PRIORITY_T1_FQ_OFST (6)
+
+#define INT_PRIORITY_PS(base_addr) (INT_CTRL00_TYPE (base_addr + 0xA8 ))
+#define INT_PRIORITY_PS_PRI_MSK (0x3F)
+#define INT_PRIORITY_PS_PRI_OFST (0)
+#define INT_PRIORITY_PS_FQ_MSK (0x40)
+#define INT_PRIORITY_PS_FQ_OFST (6)
+
+#define INT_PRIORITY_EE(base_addr) (INT_CTRL00_TYPE (base_addr + 0xAC ))
+#define INT_PRIORITY_EE_PRI_MSK (0x3F)
+#define INT_PRIORITY_EE_PRI_OFST (0)
+#define INT_PRIORITY_EE_FQ_MSK (0x40)
+#define INT_PRIORITY_EE_FQ_OFST (6)
+
+#define INT_PRIORITY_PE(base_addr) (INT_CTRL00_TYPE (base_addr + 0xB0 ))
+#define INT_PRIORITY_PE_PRI_MSK (0x3F)
+#define INT_PRIORITY_PE_PRI_OFST (0)
+#define INT_PRIORITY_PE_FQ_MSK (0x40)
+#define INT_PRIORITY_PE_FQ_OFST (6)
+
+#define INT_PRIORITY_AE(base_addr) (INT_CTRL00_TYPE (base_addr + 0xB4 ))
+#define INT_PRIORITY_AE_PRI_MSK (0x3F)
+#define INT_PRIORITY_AE_PRI_OFST (0)
+#define INT_PRIORITY_AE_FQ_MSK (0x40)
+#define INT_PRIORITY_AE_FQ_OFST (6)
+
+#define INT_PRIORITY_M0(base_addr) (INT_CTRL00_TYPE (base_addr + 0xB8 ))
+#define INT_PRIORITY_M0_PRI_MSK (0x3F)
+#define INT_PRIORITY_M0_PRI_OFST (0)
+#define INT_PRIORITY_M0_FQ_MSK (0x40)
+#define INT_PRIORITY_M0_FQ_OFST (6)
+
+#define INT_PRIORITY_M1(base_addr) (INT_CTRL00_TYPE (base_addr + 0xBC ))
+#define INT_PRIORITY_M1_PRI_MSK (0x3F)
+#define INT_PRIORITY_M1_PRI_OFST (0)
+#define INT_PRIORITY_M1_FQ_MSK (0x40)
+#define INT_PRIORITY_M1_FQ_OFST (6)
+
+#define INT_PRIORITY_FC(base_addr) (INT_CTRL00_TYPE (base_addr + 0xC0 ))
+#define INT_PRIORITY_FC_PRI_MSK (0x3F)
+#define INT_PRIORITY_FC_PRI_OFST (0)
+#define INT_PRIORITY_FC_FQ_MSK (0x40)
+#define INT_PRIORITY_FC_FQ_OFST (6)
+
+#endif /* __INT_CTRL00_H */
+
+
--- /dev/null
+#ifndef __IO_CTRL00_H
+#define __IO_CTRL00_H
+
+/*
+ * Register definitions for the I/O Control
+ */
+
+/*
+ * Copyright (c) 2000-2002 Altera Corporation, San Jose, California, USA.
+ * All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * This agreement shall be governed in all respects by the laws of the State
+ * of California and by the laws of the United States of America.
+ */
+
+#define IOCR_SDRAM(base_addr) (IO_CTRL00_TYPE (base_addr + 0x0 ))
+#define IOCR_SDRAM_LK_MSK (0x1)
+#define IOCR_SDRAM_LK_OFST (0)
+#define IOCR_SDRAM_IO_MSK (0x2)
+#define IOCR_SDRAM_IO_OFST (1)
+#define IOCR_SDRAM_OC_MSK (0x1C)
+#define IOCR_SDRAM_OC_OFST (2)
+#define IOCR_SDRAM_IC_MSK (0x60)
+#define IOCR_SDRAM_IC_OFST (5)
+
+#define IOCR_EBI(base_addr) (IO_CTRL00_TYPE (base_addr + 0x4 ))
+#define IOCR_EBI_LK_MSK (0x1)
+#define IOCR_EBI_LK_OFST (0)
+#define IOCR_EBI_IO_MSK (0x2)
+#define IOCR_EBI_IO_OFST (1)
+#define IOCR_EBI_OC_MSK (0x1C)
+#define IOCR_EBI_OC_OFST (2)
+#define IOCR_EBI_IC_MSK (0x60)
+#define IOCR_EBI_IC_OFST (5)
+
+#define IOCR_UART(base_addr) (IO_CTRL00_TYPE (base_addr + 0x8 ))
+#define IOCR_UART_LK_MSK (0x1)
+#define IOCR_UART_LK_OFST (0)
+#define IOCR_UART_IO_MSK (0x2)
+#define IOCR_UART_IO_OFST (1)
+#define IOCR_UART_OC_MSK (0x1C)
+#define IOCR_UART_OC_OFST (2)
+#define IOCR_UART_IC_MSK (0x60)
+#define IOCR_UART_IC_OFST (5)
+
+#define IOCR_TRACE(base_addr) (IO_CTRL00_TYPE (base_addr + 0xC ))
+#define IOCR_TRACE_LK_MSK (0x1)
+#define IOCR_TRACE_LK_OFST (0)
+#define IOCR_TRACE_IO_MSK (0x2)
+#define IOCR_TRACE_IO_OFST (1)
+#define IOCR_TRACE_OC_MSK (0x1C)
+#define IOCR_TRACE_OC_OFST (2)
+#define IOCR_TRACE_IC_MSK (0x60)
+#define IOCR_TRACE_IC_OFST (5)
+
+#define SDRAM_WIDTH(base_addr) (IO_CTRL00_TYPE (base_addr + 0x7C ))
+#define SDRAM_WIDTH_LK_MSK (0x1)
+#define SDRAM_WIDTH_LK_OFST (0)
+#define SDRAM_WIDTH_W_MSK (0x2)
+#define SDRAM_WIDTH_W_OFST (1)
+
+#endif /* __IO_CTRL00_H */
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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--- /dev/null
+#ifndef __MMAP00_H
+#define __MMAP00_H
+
+/*
+ * Register definitions to configure the memory map
+ */
+
+/*
+ * Copyright (c) 2000-2002 Altera Corporation, San Jose, California, USA.
+ * All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * This agreement shall be governed in all respects by the laws of the State
+ * of California and by the laws of the United States of America.
+ */
+
+#ifndef MMAP00_TYPE
+#define MMAP00_TYPE
+#warning MMAP00_TYPE not defined
+#endif
+
+#define MMAP_REGISTERS(base_addr) (MMAP00_TYPE (base_addr ))
+#define MMAP_REGISTERS_EN_MSK (0x1)
+#define MMAP_REGISTERS_EN_OFST (0x0)
+#define MMAP_REGISTERS_EN_ENABLE (0x1)
+#define MMAP_REGISTERS_NP_MSK (0x2)
+#define MMAP_REGISTERS_NP_OFST (0x1)
+#define MMAP_REGISTERS_NP_NO_PREFETCH (0x2)
+#define MMAP_REGISTERS_SIZE_MSK (0xF80)
+#define MMAP_REGISTERS_SIZE_OFST (0x7)
+#define MMAP_REGISTERS_BASE_MSK (0xFFFFC000)
+#define MMAP_REGISTERS_BASE_OFST (0xE)
+
+#define MMAP_SRAM0(base_addr) (MMAP00_TYPE (base_addr + 0x10 ))
+#define MMAP_SRAM0_EN_MSK (0x1)
+#define MMAP_SRAM0_EN_OFST (0x0)
+#define MMAP_SRAM0_EN_ENABLE (0x1)
+#define MMAP_SRAM0_NP_MSK (0x2)
+#define MMAP_SRAM0_NP_OFST (0x1)
+#define MMAP_SRAM0_NP_NO_PREFETCH (0x2)
+#define MMAP_SRAM0_SIZE_MSK (0xF80)
+#define MMAP_SRAM0_SIZE_OFST (0x7)
+#define MMAP_SRAM0_BASE_MSK (0xFFFFC000)
+#define MMAP_SRAM0_BASE_OFST (0xE)
+
+#define MMAP_SRAM1(base_addr) (MMAP00_TYPE (base_addr + 0x14 ))
+#define MMAP_SRAM1_EN_MSK (0x1)
+#define MMAP_SRAM1_EN_OFST (0x0)
+#define MMAP_SRAM1_EN_ENABLE (0x1)
+#define MMAP_SRAM1_NP_MSK (0x2)
+#define MMAP_SRAM1_NP_OFST (0x1)
+#define MMAP_SRAM1_NP_NO_PREFETCH (0x2)
+#define MMAP_SRAM1_SIZE_MSK (0xF80)
+#define MMAP_SRAM1_SIZE_OFST (0x7)
+#define MMAP_SRAM1_BASE_MSK (0xFFFFC000)
+#define MMAP_SRAM1_BASE_OFST (0xE)
+
+#define MMAP_DPSRAM0(base_addr) (MMAP00_TYPE (base_addr + 0x20 ))
+#define MMAP_DPSRAM0_EN_MSK (0x1)
+#define MMAP_DPSRAM0_EN_OFST (0x0)
+#define MMAP_DPSRAM0_EN_ENABLE (0x1)
+#define MMAP_DPSRAM0_NP_MSK (0x2)
+#define MMAP_DPSRAM0_NP_OFST (0x1)
+#define MMAP_DPSRAM0_NP_NO_PREFETCH (0x2)
+#define MMAP_DPSRAM0_SIZE_MSK (0xF80)
+#define MMAP_DPSRAM0_SIZE_OFST (0x7)
+#define MMAP_DPSRAM0_BASE_MSK (0xFFFFC000)
+#define MMAP_DPSRAM0_BASE_OFST (0xE)
+
+#define MMAP_DPSRAM1(base_addr) (MMAP00_TYPE (base_addr + 0x24 ))
+#define MMAP_DPSRAM1_EN_MSK (0x1)
+#define MMAP_DPSRAM1_EN_OFST (0x0)
+#define MMAP_DPSRAM1_EN_ENABLE (0x1)
+#define MMAP_DPSRAM1_NP_MSK (0x2)
+#define MMAP_DPSRAM1_NP_OFST (0x1)
+#define MMAP_DPSRAM1_NP_NO_PREFETCH (0x2)
+#define MMAP_DPSRAM1_SIZE_MSK (0xF80)
+#define MMAP_DPSRAM1_SIZE_OFST (0x7)
+#define MMAP_DPSRAM1_BASE_MSK (0xFFFFC000)
+#define MMAP_DPSRAM1_BASE_OFST (0xE)
+
+#define MMAP_SDRAM0(base_addr) (MMAP00_TYPE (base_addr + 0x30 ))
+#define MMAP_SDRAM0_EN_MSK (0x1)
+#define MMAP_SDRAM0_EN_OFST (0x0)
+#define MMAP_SDRAM0_EN_ENABLE (0x1)
+#define MMAP_SDRAM0_NP_MSK (0x2)
+#define MMAP_SDRAM0_NP_OFST (0x1)
+#define MMAP_SDRAM0_NP_NO_PREFETCH (0x2)
+#define MMAP_SDRAM0_SIZE_MSK (0xF80)
+#define MMAP_SDRAM0_SIZE_OFST (0x7)
+#define MMAP_SDRAM0_BASE_MSK (0xFFFFC000)
+#define MMAP_SDRAM0_BASE_OFST (0xE)
+
+#define MMAP_SDRAM1(base_addr) (MMAP00_TYPE (base_addr + 0x34 ))
+#define MMAP_SDRAM1_EN_MSK (0x1)
+#define MMAP_SDRAM1_EN_OFST (0x0)
+#define MMAP_SDRAM1_EN_ENABLE (0x1)
+#define MMAP_SDRAM1_NP_MSK (0x2)
+#define MMAP_SDRAM1_NP_OFST (0x1)
+#define MMAP_SDRAM1_NP_NO_PREFETCH (0x2)
+#define MMAP_SDRAM1_SIZE_MSK (0xF80)
+#define MMAP_SDRAM1_SIZE_OFST (0x7)
+#define MMAP_SDRAM1_BASE_MSK (0xFFFFC000)
+#define MMAP_SDRAM1_BASE_OFST (0xE)
+
+#define MMAP_EBI0(base_addr) (MMAP00_TYPE (base_addr + 0x40 ))
+#define MMAP_EBI0_EN_MSK (0x1)
+#define MMAP_EBI0_EN_OFST (0x0)
+#define MMAP_EBI0_EN_ENABLE (0x1)
+#define MMAP_EBI0_NP_MSK (0x2)
+#define MMAP_EBI0_NP_OFST (0x1)
+#define MMAP_EBI0_NP_NO_PREFETCH (0x2)
+#define MMAP_EBI0_SIZE_MSK (0xF80)
+#define MMAP_EBI0_SIZE_OFST (0x7)
+#define MMAP_EBI0_BASE_MSK (0xFFFFC000)
+#define MMAP_EBI0_BASE_OFST (0xE)
+
+#define MMAP_EBI1(base_addr) (MMAP00_TYPE (base_addr + 0x44 ))
+#define MMAP_EBI1_EN_MSK (0x1)
+#define MMAP_EBI1_EN_OFST (0x0)
+#define MMAP_EBI1_EN_ENABLE (0x1)
+#define MMAP_EBI1_NP_MSK (0x2)
+#define MMAP_EBI1_NP_OFST (0x1)
+#define MMAP_EBI1_NP_NO_PREFETCH (0x2)
+#define MMAP_EBI1_SIZE_MSK (0xF80)
+#define MMAP_EBI1_SIZE_OFST (0x7)
+#define MMAP_EBI1_BASE_MSK (0xFFFFC000)
+#define MMAP_EBI1_BASE_OFST (0xE)
+
+#define MMAP_EBI2(base_addr) (MMAP00_TYPE (base_addr + 0x48 ))
+#define MMAP_EBI2_EN_MSK (0x1)
+#define MMAP_EBI2_EN_OFST (0x0)
+#define MMAP_EBI2_EN_ENABLE (0x1)
+#define MMAP_EBI2_NP_MSK (0x2)
+#define MMAP_EBI2_NP_OFST (0x1)
+#define MMAP_EBI2_NP_NO_PREFETCH (0x2)
+#define MMAP_EBI2_SIZE_MSK (0xF80)
+#define MMAP_EBI2_SIZE_OFST (0x7)
+#define MMAP_EBI2_BASE_MSK (0xFFFFC000)
+#define MMAP_EBI2_BASE_OFST (0xE)
+
+#define MMAP_EBI3(base_addr) (MMAP00_TYPE (base_addr + 0x4C ))
+#define MMAP_EBI3_EN_MSK (0x1)
+#define MMAP_EBI3_EN_OFST (0x0)
+#define MMAP_EBI3_EN_ENABLE (0x1)
+#define MMAP_EBI3_NP_MSK (0x2)
+#define MMAP_EBI3_NP_OFST (0x1)
+#define MMAP_EBI3_NP_NO_PREFETCH (0x2)
+#define MMAP_EBI3_SIZE_MSK (0xF80)
+#define MMAP_EBI3_SIZE_OFST (0x7)
+#define MMAP_EBI3_BASE_MSK (0xFFFFC000)
+#define MMAP_EBI3_BASE_OFST (0xE)
+
+#define MMAP_PLD0(base_addr) (MMAP00_TYPE (base_addr + 0x50 ))
+#define MMAP_PLD0_EN_MSK (0x1)
+#define MMAP_PLD0_EN_OFST (0x0)
+#define MMAP_PLD0_EN_ENABLE (0x1)
+#define MMAP_PLD0_NP_MSK (0x2)
+#define MMAP_PLD0_NP_OFST (0x1)
+#define MMAP_PLD0_NP_NO_PREFETCH (0x2)
+#define MMAP_PLD0_SIZE_MSK (0xF80)
+#define MMAP_PLD0_SIZE_OFST (0x7)
+#define MMAP_PLD0_BASE_MSK (0xFFFFC000)
+#define MMAP_PLD0_BASE_OFST (0xE)
+
+#define MMAP_PLD1(base_addr) (MMAP00_TYPE (base_addr + 0x54 ))
+#define MMAP_PLD1_EN_MSK (0x1)
+#define MMAP_PLD1_EN_OFST (0x0)
+#define MMAP_PLD1_EN_ENABLE (0x1)
+#define MMAP_PLD1_NP_MSK (0x2)
+#define MMAP_PLD1_NP_OFST (0x1)
+#define MMAP_PLD1_NP_NO_PREFETCH (0x2)
+#define MMAP_PLD1_SIZE_MSK (0xF80)
+#define MMAP_PLD1_SIZE_OFST (0x7)
+#define MMAP_PLD1_BASE_MSK (0xFFFFC000)
+#define MMAP_PLD1_BASE_OFST (0xE)
+
+#define MMAP_PLD2(base_addr) (MMAP00_TYPE (base_addr + 0x58 ))
+#define MMAP_PLD2_EN_MSK (0x1)
+#define MMAP_PLD2_EN_OFST (0x0)
+#define MMAP_PLD2_EN_ENABLE (0x1)
+#define MMAP_PLD2_NP_MSK (0x2)
+#define MMAP_PLD2_NP_OFST (0x1)
+#define MMAP_PLD2_NP_NO_PREFETCH (0x2)
+#define MMAP_PLD2_SIZE_MSK (0xF80)
+#define MMAP_PLD2_SIZE_OFST (0x7)
+#define MMAP_PLD2_BASE_MSK (0xFFFFC000)
+#define MMAP_PLD2_BASE_OFST (0xE)
+
+#define MMAP_PLD3(base_addr) (MMAP00_TYPE (base_addr + 0x5C ))
+#define MMAP_PLD3_EN_MSK (0x1)
+#define MMAP_PLD3_EN_OFST (0x0)
+#define MMAP_PLD3_EN_ENABLE (0x1)
+#define MMAP_PLD3_NP_MSK (0x2)
+#define MMAP_PLD3_NP_OFST (0x1)
+#define MMAP_PLD3_NP_NO_PREFETCH (0x2)
+#define MMAP_PLD3_SIZE_MSK (0xF80)
+#define MMAP_PLD3_SIZE_OFST (0x7)
+#define MMAP_PLD3_BASE_MSK (0xFFFFC000)
+#define MMAP_PLD3_BASE_OFST (0xE)
+
+#endif /* __MMAP00_H */
--- /dev/null
+#ifndef __MODE_CTRL00_H
+#define __MODE_CTRL00_H
+
+/*
+ * Register definitions for the reset and mode control
+ */
+
+/*
+ * Copyright (c) 2000-2002 Altera Corporation, San Jose, California, USA.
+ * All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * This agreement shall be governed in all respects by the laws of the State
+ * of California and by the laws of the United States of America.
+ */
+
+#define BOOT_CR(base_addr) (MODE_CTRL00_TYPE (base_addr ))
+#define BOOT_CR_BF_MSK (0x1)
+#define BOOT_CR_BF_OFST (0)
+#define BOOT_CR_HM_MSK (0x2)
+#define BOOT_CR_HM_OFST (1)
+#define BOOT_CR_RE_MSK (0x4)
+#define BOOT_CR_RE_OFST (2)
+
+#define RESET_SR(base_addr) (MODE_CTRL00_TYPE (base_addr + 0x4 ))
+#define RESET_SR_WR_MSK (0x1)
+#define RESET_SR_WR_OFST (0)
+#define RESET_SR_CR_MSK (0x2)
+#define RESET_SR_CR_OFST (1)
+#define RESET_SR_JT_MSK (0x4)
+#define RESET_SR_JT_OFST (2)
+#define RESET_SR_ER_MSK (0x8)
+#define RESET_SR_ER_OFST (3)
+
+#define ID_CODE(base_addr) (MODE_CTRL00_TYPE (base_addr + 0x08 ))
+
+#define SRAM0_SR(base_addr) (MODE_CTRL00_TYPE (base_addr + 0x20 ))
+#define SRAM0_SR_SIZE_MSK (0xFFFFF000)
+#define SRAM0_SR_SIZE_OFST (12)
+
+#define SRAM1_SR(base_addr) (MODE_CTRL00_TYPE (base_addr + 0x24 ))
+#define SRAM1_SR_SIZE_MSK (0xFFFFF000)
+#define SRAM1_SR_SIZE_OFST (12)
+
+#define DPSRAM0_SR(base_addr) (MODE_CTRL00_TYPE (base_addr + 0x30 ))
+
+#define DPSRAM0_SR_MODE_MSK (0xF)
+#define DPSRAM0_SR_MODE_OFST (0)
+#define DPSRAM0_SR_GLBL_MSK (0x30)
+#define DPSRAM0_SR_SIZE_MSK (0xFFFFF000)
+#define DPSRAM0_SR_SIZE_OFST (12)
+
+#define DPSRAM0_LCR(base_addr) (MODE_CTRL00_TYPE (base_addr + 0x34 ))
+#define DPSRAM0_LCR_LCKADDR_MSK (0x1FFE0)
+#define DPSRAM0_LCR_LCKADDR_OFST (4)
+
+#define DPSRAM1_SR(base_addr) (MODE_CTRL00_TYPE (base_addr + 0x38 ))
+#define DPSRAM1_SR_MODE_MSK (0xF)
+#define DPSRAM1_SR_MODE_OFST (0)
+#define DPSRAM1_SR_GLBL_MSK (0x30)
+#define DPSRAM1_SR_GLBL_OFST (4)
+#define DPSRAM1_SR_SIZE_MSK (0xFFFFF000)
+#define DPSRAM1_SR_SIZE_OFST (12)
+
+#define DPSRAM1_LCR(base_addr) (MODE_CTRL00_TYPE (base_addr + 0x3C ))
+#define DPSRAM1_LCR_LCKADDR_MSK (0x1FFE0)
+#define DPSRAM1_LCR_LCKADDR_OFST (4)
+
+#endif /* __MODE_CTRL00_H */
--- /dev/null
+#ifndef __SDRAM00_H\r
+#define __SDRAM00_H\r
+\r
+/*\r
+ * Register definitions for the SDRAM Interface\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2000-2002 Altera Corporation, San Jose, California, USA. \r
+ * All rights reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy\r
+ * of this software and associated documentation files (the "Software"), to \r
+ * deal in the Software without restriction, including without limitation the \r
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r
+ * sell copies of the Software, and to permit persons to whom the Software is \r
+ * furnished to do so, subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in \r
+ * all copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR \r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, \r
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\r
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER \r
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING \r
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER \r
+ * DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * This agreement shall be governed in all respects by the laws of the State \r
+ * of California and by the laws of the United States of America.\r
+ */\r
+ \r
+#define SDRAM_TIMING1(base_addr) (SDRAM00_TYPE (base_addr + 0x0 ))\r
+#define SDRAM_TIMING1_WR_MSK (0x7)\r
+#define SDRAM_TIMING1_WR_OFST (0)\r
+#define SDRAM_TIMING1_RP_MSK (0x38)\r
+#define SDRAM_TIMING1_RP_OFST (3)\r
+#define SDRAM_TIMING1_RRD_MSK (0x1C0)\r
+#define SDRAM_TIMING1_RRD_OFST (6)\r
+#define SDRAM_TIMING1_RAS_MSK (0x1E00)\r
+#define SDRAM_TIMING1_RAS_OFST (9)\r
+#define SDRAM_TIMING1_RCD_MSK (0x7000)\r
+#define SDRAM_TIMING1_RCD_OFST (13)\r
+\r
+#define SDRAM_TIMING2(base_addr) (SDRAM00_TYPE (base_addr + 0x4 ))\r
+#define SDRAM_TIMING2_RFC_MSK (0x78)\r
+#define SDRAM_TIMING2_RFC_OFST (3)\r
+#define SDRAM_TIMING2_BL_MSK (0x180)\r
+#define SDRAM_TIMING2_BL_OFST (7)\r
+#define SDRAM_TIMING2_CL_MSK (0xE00)\r
+#define SDRAM_TIMING2_CL_OFST (9)\r
+#define SDRAM_TIMING2_RC_MSK (0xF000)\r
+#define SDRAM_TIMING2_RC_OFST (12)\r
+\r
+#define SDRAM_CONFIG(base_addr) (SDRAM00_TYPE (base_addr + 0x8 ))\r
+#define SDRAM_CONFIG_MT_MSK (0x8000)\r
+#define SDRAM_CONFIG_MT_OFST (15)\r
+\r
+#define SDRAM_REFRESH(base_addr) (SDRAM00_TYPE (base_addr + 0xC ))\r
+#define SDRAM_REFRESH_RFSH_MSK (0xFFFF)\r
+#define SDRAM_REFRESH_RFSH_OFST (0)\r
+\r
+#define SDRAM_ADDR(base_addr) (SDRAM00_TYPE (base_addr + 0x10 ))\r
+#define SDRAM_ADDR_BA_MSK (0xC0)\r
+#define SDRAM_ADDR_BA_OFST (6)\r
+#define SDRAM_ADDR_COL_MSK (0xF00)\r
+#define SDRAM_ADDR_COL_OFST (8)\r
+#define SDRAM_ADDR_ROW_MSK (0xF000)\r
+#define SDRAM_ADDR_ROW_OFST (12)\r
+\r
+#define SDRAM_BUS1(base_addr) (SDRAM00_TYPE (base_addr + 0x14 ))\r
+#define SDRAM_BUS1_BM_MSK (0xF000)\r
+#define SDRAM_BUS1_BM_OFST (15)\r
+\r
+#define SDRAM_BUS2(base_addr) (SDRAM00_TYPE (base_addr + 0x18 ))\r
+#define SDRAM_BUS2_BM_MSK (0xF000)\r
+#define SDRAM_BUS2_BM_OFST (15)\r
+\r
+#define SDRAM_INIT(base_addr) (SDRAM00_TYPE (base_addr + 0x1C ))\r
+#define SDRAM_INIT_SR_MSK (0x200)\r
+#define SDRAM_INIT_SR_OFST (9)\r
+#define SDRAM_INIT_BS_MSK (0x400)\r
+#define SDRAM_INIT_BS_OFST (10)\r
+#define SDRAM_INIT_RF_MSK (0x800)\r
+#define SDRAM_INIT_RF_OFST (11)\r
+#define SDRAM_INIT_LEM_MSK (0x1000)\r
+#define SDRAM_INIT_LEM_OFST (12)\r
+#define SDRAM_INIT_LM_MSK (0x2000)\r
+#define SDRAM_INIT_LM_OFST (13)\r
+#define SDRAM_INIT_PR_MSK (0x4000)\r
+#define SDRAM_INIT_PR_OFST (14)\r
+#define SDRAM_INIT_EN_MSK (0x8000)\r
+#define SDRAM_INIT_EN_OFST (15)\r
+\r
+#define SDRAM_MODE0(base_addr) (SDRAM00_TYPE (base_addr + 0x20 ))\r
+#define SDRAM_MODE0_VAL_MSK (0xFFF)\r
+#define SDRAM_MODE0_VAL_OFST (0)\r
+\r
+#define SDRAM_MODE1(base_addr) (SDRAM00_TYPE (base_addr + 0x24 ))\r
+#define SDRAM_MODE1_VAL_MSK (0xFFF)\r
+#define SDRAM_MODE1_VAL_OFST (0)\r
+\r
+#endif /* __SDRAM00_H */\r
--- /dev/null
+#ifndef __TIMER00_H
+#define __TIMER00_H
+
+/*
+ * Register definitions for the timers
+ */
+
+/*
+ * Copyright (c) 2000-2002 Altera Corporation, San Jose, California, USA.
+ * All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * This agreement shall be governed in all respects by the laws of the State
+ * of California and by the laws of the United States of America.
+ */
+
+#define TIMER0_CR(base_addr) (TIMER00_TYPE (base_addr + 0x00 ))
+#define TIMER0_CR_B_MSK (0x20)
+#define TIMER0_CR_B_OFST (0x5)
+#define TIMER0_CR_S_MSK (0x10)
+#define TIMER0_CR_S_OFST (0x4)
+#define TIMER0_CR_CI_MSK (0x08)
+#define TIMER0_CR_CI_OFST (0x3)
+#define TIMER0_CR_IE_MSK (0x04)
+#define TIMER0_CR_IE_OFST (0x2)
+#define TIMER0_CR_MODE_MSK (0x3)
+#define TIMER0_CR_MODE_OFST (0)
+#define TIMER0_CR_MODE_FREE (0)
+#define TIMER0_CR_MODE_ONE (1)
+#define TIMER0_CR_MODE_INTVL (2)
+
+#define TIMER0_SR(base_addr) (TIMER00_TYPE (base_addr + 0x00 ))
+#define TIMER0_SR_B_MSK (0x20)
+#define TIMER0_SR_B_OFST (0x5)
+#define TIMER0_SR_S_MSK (0x10)
+#define TIMER0_SR_S_OFST (0x4)
+#define TIMER0_SR_IS_MSK (0x08)
+#define TIMER0_SR_IS_OFST (0x3)
+#define TIMER0_SR_IE_MSK (0x04)
+#define TIMER0_SR_IE_OFST (0x2)
+#define TIMER0_SR_MODE_MSK (0x3)
+#define TIMER0_SR_MODE_OFST (0)
+#define TIMER0_SR_MODE_FREE (0)
+#define TIMER0_SR_MODE_ONE (1)
+#define TIMER0_SR_MODE_INTVL (2)
+
+#define TIMER0_PRESCALE(base_addr) (TIMER00_TYPE (base_addr + 0x010 ))
+#define TIMER0_LIMIT(base_addr) (TIMER00_TYPE (base_addr + 0x020 ))
+#define TIMER0_READ(base_addr) (TIMER00_TYPE (base_addr + 0x030 ))
+
+#define TIMER1_CR(base_addr) (TIMER00_TYPE (base_addr + 0x40 ))
+#define TIMER1_CR_B_MSK (0x20)
+#define TIMER1_CR_B_OFST (0x5)
+#define TIMER1_CR_S_MSK (0x10)
+#define TIMER1_CR_S_OFST (0x4)
+#define TIMER1_CR_CI_MSK (0x08)
+#define TIMER1_CR_CI_OFST (0x3)
+#define TIMER1_CR_IE_MSK (0x04)
+#define TIMER1_CR_IE_OFST (0x2)
+#define TIMER1_CR_MODE_MSK (0x3)
+#define TIMER1_CR_MODE_OFST (0)
+#define TIMER1_CR_MODE_FREE (0)
+#define TIMER1_CR_MODE_ONE (1)
+#define TIMER1_CR_MODE_INTVL (2)
+
+#define TIMER1_SR(base_addr) (TIMER00_TYPE (base_addr + 0x40 ))
+#define TIMER1_SR_B_MSK (0x20)
+#define TIMER1_SR_B_OFST (0x5)
+#define TIMER1_SR_S_MSK (0x10)
+#define TIMER1_SR_S_OFST (0x4)
+#define TIMER1_SR_IS_MSK (0x08)
+#define TIMER1_SR_IS_OFST (0x3)
+#define TIMER1_SR_IE_MSK (0x04)
+#define TIMER1_SR_IE_OFST (0x2)
+#define TIMER1_SR_MODE_MSK (0x3)
+#define TIMER1_SR_MODE_OFST (0)
+#define TIMER1_SR_MODE_FREE (0)
+#define TIMER1_SR_MODE_ONE (1)
+#define TIMER1_SR_MODE_INTVL (2)
+
+#define TIMER1_PRESCALE(base_addr) (TIMER00_TYPE (base_addr + 0x050 ))
+#define TIMER1_LIMIT(base_addr) (TIMER00_TYPE (base_addr + 0x060 ))
+#define TIMER1_READ(base_addr) (TIMER00_TYPE (base_addr + 0x070 ))
+
+#endif /* __TIMER00_H */
--- /dev/null
+#ifndef __UART00_H
+#define __UART00_H
+
+/*
+ * Register definitions for the UART
+ */
+
+/*
+ * Copyright (c) 2000-2002 Altera Corporation, San Jose, California, USA.
+ * All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * This agreement shall be governed in all respects by the laws of the State
+ * of California and by the laws of the United States of America.
+ */
+
+#define UART_TX_FIFO_SIZE (15)
+
+#define UART_RSR(base_addr) (UART00_TYPE (base_addr + 0x00 ))
+#define UART_RSR_RX_LEVEL_MSK (0x1f)
+#define UART_RSR_RX_LEVEL_OFST (0)
+#define UART_RSR_RE_MSK (0x80)
+#define UART_RSR_RE_OFST (7)
+
+#define UART_RDS(base_addr) (UART00_TYPE (base_addr + 0x04 ))
+#define UART_RDS_BI_MSK (0x8)
+#define UART_RDS_BI_OFST (4)
+#define UART_RDS_FE_MSK (0x4)
+#define UART_RDS_FE_OFST (2)
+#define UART_RDS_PE_MSK (0x2)
+#define UART_RDS_PE_OFST (1)
+#define UART_RDS_OE_MSK (0x1)
+#define UART_RDS_OE_OFST (0)
+
+#define UART_RD(base_addr) (UART00_TYPE (base_addr + 0x08 ))
+#define UART_RD_RX_DATA_MSK (0xff)
+#define UART_RD_RX_DATA_OFST (0)
+
+#define UART_TSR(base_addr) (UART00_TYPE (base_addr + 0x0c ))
+#define UART_TSR_TX_LEVEL_MSK (0x1f)
+#define UART_TSR_TX_LEVEL_OFST (0)
+#define UART_TSR_TXI_MSK (0x80)
+#define UART_TSR_TXI_OFST (7)
+
+#define UART_TD(base_addr) (UART00_TYPE (base_addr + 0x10 ))
+#define UART_TD_TX_DATA_MSK (0xff)
+#define UART_TD_TX_DATA_OFST (0)
+
+#define UART_FCR(base_addr) (UART00_TYPE (base_addr + 0x14 ))
+#define UART_FCR_RX_THR_MSK (0xd0)
+#define UART_FCR_RX_THR_OFST (5)
+#define UART_FCR_RX_THR_1 (0x00)
+#define UART_FCR_RX_THR_2 (0x20)
+#define UART_FCR_RX_THR_4 (0x40)
+#define UART_FCR_RX_THR_6 (0x60)
+#define UART_FCR_RX_THR_8 (0x80)
+#define UART_FCR_RX_THR_10 (0xa0)
+#define UART_FCR_RX_THR_12 (0xc0)
+#define UART_FCR_RX_THR_14 (0xd0)
+#define UART_FCR_TX_THR_MSK (0x1c)
+#define UART_FCR_TX_THR_OFST (2)
+#define UART_FCR_TX_THR_0 (0x00)
+#define UART_FCR_TX_THR_2 (0x04)
+#define UART_FCR_TX_THR_4 (0x08)
+#define UART_FCR_TX_THR_8 (0x0c)
+#define UART_FCR_TX_THR_10 (0x10)
+#define UART_FCR_TX_THR_12 (0x14)
+#define UART_FCR_TX_THR_14 (0x18)
+#define UART_FCR_TX_THR_15 (0x1c)
+#define UART_FCR_RC_MSK (0x02)
+#define UART_FCR_RC_OFST (1)
+#define UART_FCR_TC_MSK (0x01)
+#define UART_FCR_TC_OFST (0)
+
+#define UART_IES(base_addr) (UART00_TYPE (base_addr + 0x18 ))
+#define UART_IES_ME_MSK (0x8)
+#define UART_IES_ME_OFST (3)
+#define UART_IES_TIE_MSK (0x4)
+#define UART_IES_TIE_OFST (2)
+#define UART_IES_TE_MSK (0x2)
+#define UART_IES_TE_OFST (1)
+#define UART_IES_RE_MSK (0x1)
+#define UART_IES_RE_OFST (0)
+
+#define UART_IEC(base_addr) (UART00_TYPE (base_addr + 0x1c ))
+#define UART_IEC_ME_MSK (0x8)
+#define UART_IEC_ME_OFST (3)
+#define UART_IEC_TIE_MSK (0x4)
+#define UART_IEC_TIE_OFST (2)
+#define UART_IEC_TE_MSK (0x2)
+#define UART_IEC_TE_OFST (1)
+#define UART_IEC_RE_MSK (0x1)
+#define UART_IEC_RE_OFST (0)
+
+#define UART_ISR(base_addr) (UART00_TYPE (base_addr + 0x20 ))
+#define UART_ISR_MI_MSK (0x8)
+#define UART_ISR_MI_OFST (3)
+#define UART_ISR_TII_MSK (0x4)
+#define UART_ISR_TII_OFST (2)
+#define UART_ISR_TI_MSK (0x2)
+#define UART_ISR_TI_OFST (1)
+#define UART_ISR_RI_MSK (0x1)
+#define UART_ISR_RI_OFST (0)
+
+#define UART_IID(base_addr) (UART00_TYPE (base_addr + 0x24 ))
+#define UART_IID_IID_MSK (0x7)
+#define UART_IID_IID_OFST (0)
+#define UART_IID_IID_RI (1)
+#define UART_IID_IID_TI (2)
+#define UART_IID_IID_TII (3)
+#define UART_IID_IID_MI (4)
+
+#define UART_MC(base_addr) (UART00_TYPE (base_addr + 0x28 ))
+#define UART_MC_OE_MSK (0x40)
+#define UART_MC_OE_OFST (6)
+#define UART_MC_SP_MSK (0x20)
+#define UART_MC_SP_OFST (5)
+#define UART_MC_EP_MSK (0x10)
+#define UART_MC_EP_OFST (4)
+#define UART_MC_PE_MSK (0x08)
+#define UART_MC_PE_OFST (3)
+#define UART_MC_ST_MSK (0x04)
+#define UART_MC_ST_ONE (0x0)
+#define UART_MC_ST_TWO (0x04)
+#define UART_MC_ST_OFST (2)
+#define UART_MC_CLS_MSK (0x03)
+#define UART_MC_CLS_OFST (0)
+#define UART_MC_CLS_CHARLEN_5 (0)
+#define UART_MC_CLS_CHARLEN_6 (1)
+#define UART_MC_CLS_CHARLEN_7 (2)
+#define UART_MC_CLS_CHARLEN_8 (3)
+
+#define UART_MCR(base_addr) (UART00_TYPE (base_addr + 0x2c ))
+#define UART_MCR_AC_MSK (0x80)
+#define UART_MCR_AC_OFST (7)
+#define UART_MCR_AR_MSK (0x40)
+#define UART_MCR_AR_OFST (6)
+#define UART_MCR_BR_MSK (0x20)
+#define UART_MCR_BR_OFST (5)
+#define UART_MCR_LB_MSK (0x10)
+#define UART_MCR_LB_OFST (4)
+#define UART_MCR_DCD_MSK (0x08)
+#define UART_MCR_DCD_OFST (3)
+#define UART_MCR_RI_MSK (0x04)
+#define UART_MCR_RI_OFST (2)
+#define UART_MCR_DTR_MSK (0x02)
+#define UART_MCR_DTR_OFST (1)
+#define UART_MCR_RTS_MSK (0x01)
+#define UART_MCR_RTS_OFST (0)
+
+#define UART_MSR(base_addr) (UART00_TYPE (base_addr + 0x30 ))
+#define UART_MSR_DCD_MSK (0x80)
+#define UART_MSR_DCD_OFST (7)
+#define UART_MSR_RI_MSK (0x40)
+#define UART_MSR_RI_OFST (6)
+#define UART_MSR_DSR_MSK (0x20)
+#define UART_MSR_DSR_OFST (5)
+#define UART_MSR_CTS_MSK (0x10)
+#define UART_MSR_CTS_OFST (4)
+#define UART_MSR_DDCD_MSK (0x08)
+#define UART_MSR_DDCD_OFST (3)
+#define UART_MSR_TERI_MSK (0x04)
+#define UART_MSR_TERI_OFST (2)
+#define UART_MSR_DDSR_MSK (0x02)
+#define UART_MSR_DDSR_OFST (1)
+#define UART_MSR_DCTS_MSK (0x01)
+#define UART_MSR_DCTS_OFST (0)
+
+#define UART_DIV_LO(base_addr) (UART00_TYPE (base_addr + 0x34 ))
+#define UART_DIV_LO_DIV_MSK (0xff)
+#define UART_DIV_LO_DIV_OFST (0)
+
+#define UART_DIV_HI(base_addr) (UART00_TYPE (base_addr + 0x38 ))
+#define UART_DIV_HI_DIV_MSK (0xff)
+#define UART_DIV_HI_DIV_OFST (0)
+
+#endif /* __UART00_H */
--- /dev/null
+#ifndef __WATCHDOG_00_H\r
+#define __WATCHDOG_00_H\r
+\r
+/*\r
+ * Register definitions for the watchdog\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2000-2002 Altera Corporation, San Jose, California, USA. \r
+ * All rights reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy\r
+ * of this software and associated documentation files (the "Software"), to \r
+ * deal in the Software without restriction, including without limitation the \r
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or\r
+ * sell copies of the Software, and to permit persons to whom the Software is \r
+ * furnished to do so, subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in \r
+ * all copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR \r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, \r
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\r
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER \r
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING \r
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER \r
+ * DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * This agreement shall be governed in all respects by the laws of the State \r
+ * of California and by the laws of the United States of America.\r
+ */\r
+\r
+#define WDOG_CR(base_addr) (WATCHDOG00_TYPE (base_addr ))\r
+#define WDOG_CR_LK_MSK (0x1)\r
+#define WDOG_CR_LK_OFST (0)\r
+#define WDOG_CR_LK_ENABLE (0x1)\r
+#define WDOG_CR_TRIGGER_MSK (0x3FFFFFF0)\r
+#define WDOG_CR_TRIGGER_OFST (4)\r
+\r
+#define WDOG_COUNT(base_addr) (WATCHDOG00_TYPE (base_addr + 0x4 ))\r
+#define WDOG_COUNT_MSK (0x3FFFFFFF)\r
+\r
+#define WDOG_RELOAD(base_addr) (WATCHDOG00_TYPE (base_addr + 0x8 )) \r
+#define WDOG_RELOAD_MAGIC_1 (0xA5A5A5A5)\r
+#define WDOG_RELOAD_MAGIC_2 (0x5A5A5A5A)\r
+\r
+#endif /* __WATCHDOG_00_H */\r
#define INTEL_ID_28F160B3B 0x88918891 /* 16M = 1M x 16 bottom boot sector */
#define INTEL_ID_28F320B3T 0x88968896 /* 32M = 2M x 16 top boot sector */
#define INTEL_ID_28F320C3T 0x88C488C4 /* 32M = 2M x 16 top boot sector */
+#define INTEL_ID_28F320C3B 0x88C488C5 /* 32M = 2M x 16 bottom boot sector */
#define INTEL_ID_28F320B3B 0x88978897 /* 32M = 2M x 16 bottom boot sector */
#define INTEL_ID_28F640B3T 0x88988898 /* 64M = 4M x 16 top boot sector */
#define INTEL_ID_28F640B3B 0x88998899 /* 64M = 4M x 16 bottom boot sector */
projects / users / rw / armboot.git / commitdiff