Otherwise we could (in theory) run into problems on 32bit systems.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
        struct amdgpu_sync      active;
        struct fence            *last_flush;
        struct amdgpu_ring      *last_user;
-       atomic_long_t           owner;
+       atomic64_t              owner;
 
        uint64_t                pd_gpu_addr;
        /* last flushed PD/PT update */
 
                if (!id)
                        continue;
 
-               if (atomic_long_read(&id->owner) != vm->client_id)
+               if (atomic64_read(&id->owner) != vm->client_id)
                        continue;
 
                if (pd_addr != id->pd_gpu_addr)
 
        list_move_tail(&id->list, &adev->vm_manager.ids_lru);
        id->last_user = ring;
-       atomic_long_set(&id->owner, vm->client_id);
+       atomic64_set(&id->owner, vm->client_id);
        vm->ids[ring->idx] = id;
 
        *vm_id = id - adev->vm_manager.ids;