x86/PCI: Add support for the Intel 82426EX PIRQ router

The Intel 82426EX ISA Bridge (IB), a part of the Intel 82420EX PCIset,
implements PCI interrupt steering with a PIRQ router in the form of two
PIRQ Route Control registers, available in the PCI configuration space
at locations 0x66 and 0x67 for the PIRQ0# and PIRQ1# lines respectively.

The semantics is the same as with the PIIX router, however it is not
clear if BIOSes use register indices or line numbers as the cookie to
identify PCI interrupts in their routing tables and therefore support
either scheme.

The IB is directly attached to the Intel 82425EX PCI System Controller
(PSC) component of the chipset via a dedicated PSC/IB Link interface
rather than the host bus or PCI.  Therefore it does not itself appear in
the PCI configuration space even though it responds to configuration
cycles addressing registers it implements.  Use 82425EX's identification
then for determining the presence of the IB.

References:

[1] "82420EX PCIset Data Sheet, 82425EX PCI System Controller (PSC) and
    82426EX ISA Bridge (IB)", Intel Corporation, Order Number:
    290488-004, December 1995, Section 3.3.18 "PIRQ1RC/PIRQ0RC--PIRQ
    Route Control Registers", p. 61

Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/alpine.DEB.2.21.2107200213490.9461@angie.orcam.me.uk

diff --git a/arch/x86/pci/irq.c b/arch/x86/pci/irq.c
index 187e284f2021ab95c623132389b0991c6ca43841..b937c96f9f85f4654587acdac8e2ca77579dfa08 100644 (file)
--- a/arch/x86/pci/irq.c
+++ b/arch/x86/pci/irq.c
@@ -443,6 +443,50 @@ static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq,
        return 1;
 }
 
+/*
+ *     PIRQ routing for the 82426EX ISA Bridge (IB) ASIC used with the
+ *     Intel 82420EX PCIset.
+ *
+ *     There are only two PIRQ Route Control registers, available in the
+ *     combined 82425EX/82426EX PCI configuration space, at 0x66 and 0x67
+ *     for the PIRQ0# and PIRQ1# lines respectively.  The semantics is
+ *     the same as with the PIIX router.
+ *
+ *     References:
+ *
+ *     "82420EX PCIset Data Sheet, 82425EX PCI System Controller (PSC)
+ *     and 82426EX ISA Bridge (IB)", Intel Corporation, Order Number:
+ *     290488-004, December 1995
+ */
+
+#define PCI_I82426EX_PIRQ_ROUTE_CONTROL        0x66u
+
+static int pirq_ib_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
+{
+       int reg;
+       u8 x;
+
+       reg = pirq;
+       if (reg >= 1 && reg <= 2)
+               reg += PCI_I82426EX_PIRQ_ROUTE_CONTROL - 1;
+
+       pci_read_config_byte(router, reg, &x);
+       return (x < 16) ? x : 0;
+}
+
+static int pirq_ib_set(struct pci_dev *router, struct pci_dev *dev, int pirq,
+                      int irq)
+{
+       int reg;
+
+       reg = pirq;
+       if (reg >= 1 && reg <= 2)
+               reg += PCI_I82426EX_PIRQ_ROUTE_CONTROL - 1;
+
+       pci_write_config_byte(router, reg, irq);
+       return 1;
+}
+
 /*
  * The VIA pirq rules are nibble-based, like ALI,
  * but without the ugly irq number munging.
@@ -805,6 +849,11 @@ static __init int intel_router_probe(struct irq_router *r, struct pci_dev *route
                r->get = pirq_piix_get;
                r->set = pirq_piix_set;
                return 1;
+       case PCI_DEVICE_ID_INTEL_82425:
+               r->name = "PSC/IB";
+               r->get = pirq_ib_get;
+               r->set = pirq_ib_set;
+               return 1;
        }
 
        if ((device >= PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MIN && 

diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 256fa4d7e86c9b559fc72f01bdb7ebc03ecd8de1..60e2101a009d6971961e3b73ecbb2a361a177be4 100644 (file)
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2644,6 +2644,7 @@
 #define PCI_DEVICE_ID_INTEL_82375      0x0482
 #define PCI_DEVICE_ID_INTEL_82424      0x0483
 #define PCI_DEVICE_ID_INTEL_82378      0x0484
+#define PCI_DEVICE_ID_INTEL_82425      0x0486
 #define PCI_DEVICE_ID_INTEL_MRST_SD0   0x0807
 #define PCI_DEVICE_ID_INTEL_MRST_SD1   0x0808
 #define PCI_DEVICE_ID_INTEL_MFD_SD     0x0820