]> www.infradead.org Git - users/jedix/linux-maple.git/commitdiff
clk: qcom: alpha-pll: convert from round_rate() to determine_rate()
authorBrian Masney <bmasney@redhat.com>
Fri, 29 Aug 2025 00:38:21 +0000 (20:38 -0400)
committerBjorn Andersson <andersson@kernel.org>
Thu, 4 Sep 2025 13:36:27 +0000 (08:36 -0500)
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.

Note that prior to running the Coccinelle,
clk_alpha_pll_postdiv_round_ro_rate() was renamed to
clk_alpha_pll_postdiv_ro_round_rate().

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
Link: https://lore.kernel.org/r/20250828-clk-round-rate-v2-v1-2-b97ec8ba6cc4@redhat.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
drivers/clk/qcom/clk-alpha-pll.c

index 81a1ce42285f7eb19dba92cb7415c7e694a829dd..6aeba40358c11e44c5f39d15f149d62149393cd3 100644 (file)
@@ -849,22 +849,25 @@ static int clk_alpha_pll_hwfsm_set_rate(struct clk_hw *hw, unsigned long rate,
                                        clk_alpha_pll_hwfsm_is_enabled);
 }
 
-static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate,
-                                    unsigned long *prate)
+static int clk_alpha_pll_determine_rate(struct clk_hw *hw,
+                                       struct clk_rate_request *req)
 {
        struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
        u32 l, alpha_width = pll_alpha_width(pll);
        u64 a;
        unsigned long min_freq, max_freq;
 
-       rate = alpha_pll_round_rate(rate, *prate, &l, &a, alpha_width);
-       if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
-               return rate;
+       req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate, &l,
+                                        &a, alpha_width);
+       if (!pll->vco_table || alpha_pll_find_vco(pll, req->rate))
+               return 0;
 
        min_freq = pll->vco_table[0].min_freq;
        max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
 
-       return clamp(rate, min_freq, max_freq);
+       req->rate = clamp(req->rate, min_freq, max_freq);
+
+       return 0;
 }
 
 void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
@@ -1048,12 +1051,15 @@ static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate,
        return 0;
 }
 
-static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate,
-                                       unsigned long *prate)
+static int alpha_pll_huayra_determine_rate(struct clk_hw *hw,
+                                          struct clk_rate_request *req)
 {
        u32 l, a;
 
-       return alpha_huayra_pll_round_rate(rate, *prate, &l, &a);
+       req->rate = alpha_huayra_pll_round_rate(req->rate,
+                                               req->best_parent_rate, &l, &a);
+
+       return 0;
 }
 
 static int trion_pll_is_enabled(struct clk_alpha_pll *pll,
@@ -1175,7 +1181,7 @@ const struct clk_ops clk_alpha_pll_ops = {
        .disable = clk_alpha_pll_disable,
        .is_enabled = clk_alpha_pll_is_enabled,
        .recalc_rate = clk_alpha_pll_recalc_rate,
-       .round_rate = clk_alpha_pll_round_rate,
+       .determine_rate = clk_alpha_pll_determine_rate,
        .set_rate = clk_alpha_pll_set_rate,
 };
 EXPORT_SYMBOL_GPL(clk_alpha_pll_ops);
@@ -1185,7 +1191,7 @@ const struct clk_ops clk_alpha_pll_huayra_ops = {
        .disable = clk_alpha_pll_disable,
        .is_enabled = clk_alpha_pll_is_enabled,
        .recalc_rate = alpha_pll_huayra_recalc_rate,
-       .round_rate = alpha_pll_huayra_round_rate,
+       .determine_rate = alpha_pll_huayra_determine_rate,
        .set_rate = alpha_pll_huayra_set_rate,
 };
 EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops);
@@ -1195,7 +1201,7 @@ const struct clk_ops clk_alpha_pll_hwfsm_ops = {
        .disable = clk_alpha_pll_hwfsm_disable,
        .is_enabled = clk_alpha_pll_hwfsm_is_enabled,
        .recalc_rate = clk_alpha_pll_recalc_rate,
-       .round_rate = clk_alpha_pll_round_rate,
+       .determine_rate = clk_alpha_pll_determine_rate,
        .set_rate = clk_alpha_pll_hwfsm_set_rate,
 };
 EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);
@@ -1205,7 +1211,7 @@ const struct clk_ops clk_alpha_pll_fixed_trion_ops = {
        .disable = clk_trion_pll_disable,
        .is_enabled = clk_trion_pll_is_enabled,
        .recalc_rate = clk_trion_pll_recalc_rate,
-       .round_rate = clk_alpha_pll_round_rate,
+       .determine_rate = clk_alpha_pll_determine_rate,
 };
 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_trion_ops);
 
@@ -1240,9 +1246,8 @@ static const struct clk_div_table clk_alpha_2bit_div_table[] = {
        { }
 };
 
-static long
-clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
-                                unsigned long *prate)
+static int clk_alpha_pll_postdiv_determine_rate(struct clk_hw *hw,
+                                               struct clk_rate_request *req)
 {
        struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
        const struct clk_div_table *table;
@@ -1252,13 +1257,15 @@ clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
        else
                table = clk_alpha_div_table;
 
-       return divider_round_rate(hw, rate, prate, table,
-                                 pll->width, CLK_DIVIDER_POWER_OF_TWO);
+       req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate,
+                                      table, pll->width,
+                                      CLK_DIVIDER_POWER_OF_TWO);
+
+       return 0;
 }
 
-static long
-clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate,
-                                   unsigned long *prate)
+static int clk_alpha_pll_postdiv_ro_determine_rate(struct clk_hw *hw,
+                                                  struct clk_rate_request *req)
 {
        struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
        u32 ctl, div;
@@ -1270,9 +1277,12 @@ clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate,
        div = 1 << fls(ctl);
 
        if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)
-               *prate = clk_hw_round_rate(clk_hw_get_parent(hw), div * rate);
+               req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
+                                                         div * req->rate);
+
+       req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div);
 
-       return DIV_ROUND_UP_ULL((u64)*prate, div);
+       return 0;
 }
 
 static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -1291,13 +1301,13 @@ static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
 
 const struct clk_ops clk_alpha_pll_postdiv_ops = {
        .recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
-       .round_rate = clk_alpha_pll_postdiv_round_rate,
+       .determine_rate = clk_alpha_pll_postdiv_determine_rate,
        .set_rate = clk_alpha_pll_postdiv_set_rate,
 };
 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops);
 
 const struct clk_ops clk_alpha_pll_postdiv_ro_ops = {
-       .round_rate = clk_alpha_pll_postdiv_round_ro_rate,
+       .determine_rate = clk_alpha_pll_postdiv_ro_determine_rate,
        .recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
 };
 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops);
@@ -1542,7 +1552,7 @@ const struct clk_ops clk_alpha_pll_fabia_ops = {
        .is_enabled = clk_alpha_pll_is_enabled,
        .set_rate = alpha_pll_fabia_set_rate,
        .recalc_rate = alpha_pll_fabia_recalc_rate,
-       .round_rate = clk_alpha_pll_round_rate,
+       .determine_rate = clk_alpha_pll_determine_rate,
 };
 EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops);
 
@@ -1551,7 +1561,7 @@ const struct clk_ops clk_alpha_pll_fixed_fabia_ops = {
        .disable = alpha_pll_fabia_disable,
        .is_enabled = clk_alpha_pll_is_enabled,
        .recalc_rate = alpha_pll_fabia_recalc_rate,
-       .round_rate = clk_alpha_pll_round_rate,
+       .determine_rate = clk_alpha_pll_determine_rate,
 };
 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_fabia_ops);
 
@@ -1602,14 +1612,16 @@ clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
        return (parent_rate / div);
 }
 
-static long
-clk_trion_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
-                                unsigned long *prate)
+static int clk_trion_pll_postdiv_determine_rate(struct clk_hw *hw,
+                                               struct clk_rate_request *req)
 {
        struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
 
-       return divider_round_rate(hw, rate, prate, pll->post_div_table,
-                                 pll->width, CLK_DIVIDER_ROUND_CLOSEST);
+       req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate,
+                                      pll->post_div_table,
+                                      pll->width, CLK_DIVIDER_ROUND_CLOSEST);
+
+       return 0;
 };
 
 static int
@@ -1635,18 +1647,21 @@ clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
 
 const struct clk_ops clk_alpha_pll_postdiv_trion_ops = {
        .recalc_rate = clk_trion_pll_postdiv_recalc_rate,
-       .round_rate = clk_trion_pll_postdiv_round_rate,
+       .determine_rate = clk_trion_pll_postdiv_determine_rate,
        .set_rate = clk_trion_pll_postdiv_set_rate,
 };
 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_trion_ops);
 
-static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw,
-                               unsigned long rate, unsigned long *prate)
+static int clk_alpha_pll_postdiv_fabia_determine_rate(struct clk_hw *hw,
+                                                     struct clk_rate_request *req)
 {
        struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
 
-       return divider_round_rate(hw, rate, prate, pll->post_div_table,
-                               pll->width, CLK_DIVIDER_ROUND_CLOSEST);
+       req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate,
+                                      pll->post_div_table,
+                                      pll->width, CLK_DIVIDER_ROUND_CLOSEST);
+
+       return 0;
 }
 
 static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw,
@@ -1681,7 +1696,7 @@ static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw,
 
 const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = {
        .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
-       .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
+       .determine_rate = clk_alpha_pll_postdiv_fabia_determine_rate,
        .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
 };
 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops);
@@ -1833,7 +1848,7 @@ const struct clk_ops clk_alpha_pll_trion_ops = {
        .disable = clk_trion_pll_disable,
        .is_enabled = clk_trion_pll_is_enabled,
        .recalc_rate = clk_trion_pll_recalc_rate,
-       .round_rate = clk_alpha_pll_round_rate,
+       .determine_rate = clk_alpha_pll_determine_rate,
        .set_rate = alpha_pll_trion_set_rate,
 };
 EXPORT_SYMBOL_GPL(clk_alpha_pll_trion_ops);
@@ -1844,14 +1859,14 @@ const struct clk_ops clk_alpha_pll_lucid_ops = {
        .disable = clk_trion_pll_disable,
        .is_enabled = clk_trion_pll_is_enabled,
        .recalc_rate = clk_trion_pll_recalc_rate,
-       .round_rate = clk_alpha_pll_round_rate,
+       .determine_rate = clk_alpha_pll_determine_rate,
        .set_rate = alpha_pll_trion_set_rate,
 };
 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_ops);
 
 const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = {
        .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
-       .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
+       .determine_rate = clk_alpha_pll_postdiv_fabia_determine_rate,
        .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
 };
 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops);
@@ -1903,7 +1918,7 @@ const struct clk_ops clk_alpha_pll_agera_ops = {
        .disable = clk_alpha_pll_disable,
        .is_enabled = clk_alpha_pll_is_enabled,
        .recalc_rate = alpha_pll_fabia_recalc_rate,
-       .round_rate = clk_alpha_pll_round_rate,
+       .determine_rate = clk_alpha_pll_determine_rate,
        .set_rate = clk_alpha_pll_agera_set_rate,
 };
 EXPORT_SYMBOL_GPL(clk_alpha_pll_agera_ops);
@@ -2119,7 +2134,7 @@ const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = {
        .disable = alpha_pll_lucid_5lpe_disable,
        .is_enabled = clk_trion_pll_is_enabled,
        .recalc_rate = clk_trion_pll_recalc_rate,
-       .round_rate = clk_alpha_pll_round_rate,
+       .determine_rate = clk_alpha_pll_determine_rate,
        .set_rate = alpha_pll_lucid_5lpe_set_rate,
 };
 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_5lpe_ops);
@@ -2129,13 +2144,13 @@ const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = {
        .disable = alpha_pll_lucid_5lpe_disable,
        .is_enabled = clk_trion_pll_is_enabled,
        .recalc_rate = clk_trion_pll_recalc_rate,
-       .round_rate = clk_alpha_pll_round_rate,
+       .determine_rate = clk_alpha_pll_determine_rate,
 };
 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_5lpe_ops);
 
 const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = {
        .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
-       .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
+       .determine_rate = clk_alpha_pll_postdiv_fabia_determine_rate,
        .set_rate = clk_lucid_5lpe_pll_postdiv_set_rate,
 };
 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_5lpe_ops);
@@ -2304,7 +2319,7 @@ const struct clk_ops clk_alpha_pll_zonda_ops = {
        .disable = clk_zonda_pll_disable,
        .is_enabled = clk_trion_pll_is_enabled,
        .recalc_rate = clk_trion_pll_recalc_rate,
-       .round_rate = clk_alpha_pll_round_rate,
+       .determine_rate = clk_alpha_pll_determine_rate,
        .set_rate = clk_zonda_pll_set_rate,
 };
 EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops);
@@ -2529,13 +2544,13 @@ const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops = {
        .disable = alpha_pll_lucid_evo_disable,
        .is_enabled = clk_trion_pll_is_enabled,
        .recalc_rate = alpha_pll_lucid_evo_recalc_rate,
-       .round_rate = clk_alpha_pll_round_rate,
+       .determine_rate = clk_alpha_pll_determine_rate,
 };
 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_evo_ops);
 
 const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops = {
        .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
-       .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
+       .determine_rate = clk_alpha_pll_postdiv_fabia_determine_rate,
        .set_rate = clk_lucid_evo_pll_postdiv_set_rate,
 };
 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_evo_ops);
@@ -2546,7 +2561,7 @@ const struct clk_ops clk_alpha_pll_lucid_evo_ops = {
        .disable = alpha_pll_lucid_evo_disable,
        .is_enabled = clk_trion_pll_is_enabled,
        .recalc_rate = alpha_pll_lucid_evo_recalc_rate,
-       .round_rate = clk_alpha_pll_round_rate,
+       .determine_rate = clk_alpha_pll_determine_rate,
        .set_rate = alpha_pll_lucid_5lpe_set_rate,
 };
 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_evo_ops);
@@ -2557,7 +2572,7 @@ const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops = {
        .disable = alpha_pll_reset_lucid_evo_disable,
        .is_enabled = clk_trion_pll_is_enabled,
        .recalc_rate = alpha_pll_lucid_evo_recalc_rate,
-       .round_rate = clk_alpha_pll_round_rate,
+       .determine_rate = clk_alpha_pll_determine_rate,
        .set_rate = alpha_pll_lucid_5lpe_set_rate,
 };
 EXPORT_SYMBOL_GPL(clk_alpha_pll_reset_lucid_evo_ops);
@@ -2732,22 +2747,25 @@ static unsigned long clk_rivian_evo_pll_recalc_rate(struct clk_hw *hw,
        return parent_rate * l;
 }
 
-static long clk_rivian_evo_pll_round_rate(struct clk_hw *hw, unsigned long rate,
-                                         unsigned long *prate)
+static int clk_rivian_evo_pll_determine_rate(struct clk_hw *hw,
+                                            struct clk_rate_request *req)
 {
        struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
        unsigned long min_freq, max_freq;
        u32 l;
        u64 a;
 
-       rate = alpha_pll_round_rate(rate, *prate, &l, &a, 0);
-       if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
-               return rate;
+       req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate, &l,
+                                        &a, 0);
+       if (!pll->vco_table || alpha_pll_find_vco(pll, req->rate))
+               return 0;
 
        min_freq = pll->vco_table[0].min_freq;
        max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
 
-       return clamp(rate, min_freq, max_freq);
+       req->rate = clamp(req->rate, min_freq, max_freq);
+
+       return 0;
 }
 
 const struct clk_ops clk_alpha_pll_rivian_evo_ops = {
@@ -2755,7 +2773,7 @@ const struct clk_ops clk_alpha_pll_rivian_evo_ops = {
        .disable = alpha_pll_lucid_5lpe_disable,
        .is_enabled = clk_trion_pll_is_enabled,
        .recalc_rate = clk_rivian_evo_pll_recalc_rate,
-       .round_rate = clk_rivian_evo_pll_round_rate,
+       .determine_rate = clk_rivian_evo_pll_determine_rate,
 };
 EXPORT_SYMBOL_GPL(clk_alpha_pll_rivian_evo_ops);
 
@@ -2964,7 +2982,7 @@ const struct clk_ops clk_alpha_pll_regera_ops = {
        .disable = clk_zonda_pll_disable,
        .is_enabled = clk_alpha_pll_is_enabled,
        .recalc_rate = clk_trion_pll_recalc_rate,
-       .round_rate = clk_alpha_pll_round_rate,
+       .determine_rate = clk_alpha_pll_determine_rate,
        .set_rate = clk_zonda_pll_set_rate,
 };
 EXPORT_SYMBOL_GPL(clk_alpha_pll_regera_ops);
@@ -3169,7 +3187,7 @@ const struct clk_ops clk_alpha_pll_slew_ops = {
        .enable = clk_alpha_pll_slew_enable,
        .disable = clk_alpha_pll_disable,
        .recalc_rate = clk_alpha_pll_recalc_rate,
-       .round_rate = clk_alpha_pll_round_rate,
+       .determine_rate = clk_alpha_pll_determine_rate,
        .set_rate = clk_alpha_pll_slew_set_rate,
 };
 EXPORT_SYMBOL(clk_alpha_pll_slew_ops);