{
        struct pci_controller *hose;
        struct list_head resources;
+       struct pci_host_bridge *bridge;
        struct pci_bus *bus;
-       int next_busno;
+       int ret, next_busno;
        int need_domain_info = 0;
        u32 pci_mem_end;
        u32 sg_base;
                pci_add_resource_offset(&resources, hose->mem_space,
                                        hose->mem_space->start);
 
-               bus = pci_scan_root_bus(NULL, next_busno, alpha_mv.pci_ops,
-                                       hose, &resources);
-               if (!bus)
+               bridge = pci_alloc_host_bridge(0);
+               if (!bridge)
                        continue;
-               hose->bus = bus;
+
+               list_splice_init(&resources, &bridge->windows);
+               bridge->dev.parent = NULL;
+               bridge->sysdata = hose;
+               bridge->busnr = next_busno;
+               bridge->ops = alpha_mv.pci_ops;
+               bridge->swizzle_irq = alpha_mv.pci_swizzle;
+               bridge->map_irq = alpha_mv.pci_map_irq;
+
+               ret = pci_scan_root_bus_bridge(bridge);
+               if (ret) {
+                       pci_free_host_bridge(bridge);
+                       continue;
+               }
+
+               bus = hose->bus = bridge->bus;
                hose->need_domain_info = need_domain_info;
                next_busno = bus->busn_res.end + 1;
                /* Don't allow 8-bit bus number overflow inside the hose -
        pcibios_claim_console_setup();
 
        pci_assign_unassigned_resources();
-       pci_fixup_irqs(alpha_mv.pci_swizzle, alpha_mv.pci_map_irq);
        for (hose = hose_head; hose; hose = hose->next) {
                bus = hose->bus;
                if (bus)
        }
 }
 
-
 struct pci_controller * __init
 alloc_pci_controller(void)
 {
 
        .name   = "Irongate PCI MEM",
        .flags  = IORESOURCE_MEM,
 };
+static struct resource busn_resource = {
+       .name   = "PCI busn",
+       .start  = 0,
+       .end    = 255,
+       .flags  = IORESOURCE_BUS,
+};
 
 void __init
 nautilus_init_pci(void)
 {
        struct pci_controller *hose = hose_head;
+       struct pci_host_bridge *bridge;
        struct pci_bus *bus;
        struct pci_dev *irongate;
        unsigned long bus_align, bus_size, pci_mem;
        unsigned long memtop = max_low_pfn << PAGE_SHIFT;
+       int ret;
+
+       bridge = pci_alloc_host_bridge(0);
+       if (!bridge)
+               return;
+
+       pci_add_resource(&bridge->windows, &ioport_resource);
+       pci_add_resource(&bridge->windows, &iomem_resource);
+       pci_add_resource(&bridge->windows, &busn_resource);
+       bridge->dev.parent = NULL;
+       bridge->sysdata = hose;
+       bridge->busnr = 0;
+       bridge->ops = alpha_mv.pci_ops;
+       bridge->swizzle_irq = alpha_mv.pci_swizzle;
+       bridge->map_irq = alpha_mv.pci_map_irq;
 
        /* Scan our single hose.  */
-       bus = pci_scan_bus(0, alpha_mv.pci_ops, hose);
-       if (!bus)
+       ret = pci_scan_root_bus_bridge(bridge);
+       if (ret) {
+               pci_free_host_bridge(bridge);
                return;
+       }
 
-       hose->bus = bus;
+       bus = hose->bus = bridge->bus;
        pcibios_claim_one_bus(bus);
 
        irongate = pci_get_bus_and_slot(0, 0);
        /* pci_common_swizzle() relies on bus->self being NULL
           for the root bus, so just clear it. */
        bus->self = NULL;
-       pci_fixup_irqs(alpha_mv.pci_swizzle, alpha_mv.pci_map_irq);
        pci_bus_add_devices(bus);
 }