drm/i915/psr: Add Early Transport status boolean into intel_psr

Currently we are purely relying on psr2_su_region_et_valid. Add new boolean
value into intel_psr struct indicating whether Early Transport is enabled
or not and use it instead of psr2_su_region_et_valid for getting Early
Transport status information.

Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240529093849.1016172-2-jouni.hogander@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 52d0fd2bdc8271afe53c8665422cb2937950a2c7..77609656317b5ce0d0ba7568c1bf42cc8ac6d05a 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1706,6 +1706,7 @@ struct intel_psr {
        bool sel_update_enabled;
        bool psr2_sel_fetch_enabled;
        bool psr2_sel_fetch_cff_enabled;
+       bool su_region_et_enabled;
        bool req_psr2_sdp_prior_scanline;
        u8 sink_sync_latency;
        ktime_t last_entry_attempt;

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 4b337bcd9c90370ae079db735507ae83b264fdf0..410b51f38d482023e4745659a9eecc3b71ccfd32 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -978,7 +978,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
                               PSR2_MAN_TRK_CTL(dev_priv, cpu_transcoder), 0);
        }
 
-       if (psr2_su_region_et_valid(intel_dp))
+       if (intel_dp->psr.su_region_et_enabled)
                val |= LNL_EDP_PSR2_SU_REGION_ET_ENABLE;
 
        /*
@@ -1771,6 +1771,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
        intel_dp->psr.dc3co_exit_delay = val;
        intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
        intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
+       intel_dp->psr.su_region_et_enabled = crtc_state->enable_psr2_su_region_et;
        intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
        intel_dp->psr.req_psr2_sdp_prior_scanline =
                crtc_state->req_psr2_sdp_prior_scanline;
@@ -1927,6 +1928,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
        intel_dp->psr.panel_replay_enabled = false;
        intel_dp->psr.sel_update_enabled = false;
        intel_dp->psr.psr2_sel_fetch_enabled = false;
+       intel_dp->psr.su_region_et_enabled = false;
        intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
 }