return _SUCCESS;
 }
 
-
 static void enable_video_mode(struct _adapter *padapter, int cbw40_value)
 {
        /*   bit 8:
 
  *
  ******************************************************************************/
 
-
 #ifndef __RTL8712_BITDEF_H__
 #define __RTL8712_BITDEF_H__
 
 
 #ifndef __RTL8712_CMDCTRL_REGDEF_H__
 #define __RTL8712_CMDCTRL_REGDEF_H__
 
-
 #define CR                     (RTL8712_CMDCTRL_ + 0x0000)
 #define TXPAUSE                        (RTL8712_CMDCTRL_ + 0x0002)
 #define TCR                    (RTL8712_CMDCTRL_ + 0x0004)
 #define SYSF_CFG               (RTL8712_CMDCTRL_ + 0x000D)
 #define MBIDCTRL               (RTL8712_CMDCTRL_ + 0x000E)
 
-
 #endif /* __RTL8712_CMDCTRL_REGDEF_H__ */
 
 
 /*FDLOCKFLAG1*/
 #define        _LOCKFLAG1_MSK          0x03
 
-
 #endif /* __RTL8712_DEBUGCTRL_BITDEF_H__ */
 
 #define TRXPKTBUF_DBG_CTRL     (RTL8712_DEBUGCTRL_ + 0x38)
 #define DPLL_MON               (RTL8712_DEBUGCTRL_ + 0x3A)
 
-
-
 #endif /* __RTL8712_DEBUGCTRL_REGDEF_H__ */
 
 
 /*TXFF_PG_NUM*/
 #define        _TXFF_PG_NUM_MSK        0x0FFF
 
-
 #endif /*      __RTL8712_FIFOCTRL_BITDEF_H__ */
 
 
 #define TXQ_PGADD              (RTL8712_FIFOCTRL_ + 0xB3)
 #define TXFF_PG_NUM            (RTL8712_FIFOCTRL_ + 0xB4)
 
-
-
 #endif /* __RTL8712_FIFOCTRL_REGDEF_H__ */
 
 #define PHY_REG_RPT            (RTL8712_GP_ + 0x13)
 #define PHY_REG_DATA           (RTL8712_GP_ + 0x14)
 
-
 #endif /*__RTL8712_GP_REGDEF_H__ */
 
 
 #define        _VODOK                                  BIT(1)
 #define        _RXOK                                   BIT(0)
 
-
 #endif /*__RTL8712_INTERRUPT_BITDEF_H__*/