usb: dwc3: add support for USB 2.0-only core configuration

Newer DWC3 controllers can be built for USB 2.0-only mode, where
most of the USB 3.0 circuitry is left out. To support this mode,
the driver must limit the speed programmed into the DCFG register
to Hi-Speed or lower.

Reads and writes to the PIPECTL register are left as-is, since
they should be no-ops in USB 2.0-only mode. Calls to phy_init()
etc. for the USB3 phy are also left as-is, since the no-op USB3
phy should be used for USB 2.0-only mode controllers.

Signed-off-by: Paul Zimmerman <paulz@synopsys.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index fbe446350e28d821b481bd642135274e48597a31..b769c1faaf0385dff2543592e2fe68745d1fc7c5 100644 (file)
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -386,6 +386,13 @@ static int dwc3_core_init(struct dwc3 *dwc)
        }
        dwc->revision = reg;
 
+       /* Handle USB2.0-only core configuration */
+       if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
+                       DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
+               if (dwc->maximum_speed == USB_SPEED_SUPER)
+                       dwc->maximum_speed = USB_SPEED_HIGH;
+       }
+
        /* issue device SoftReset too */
        timeout = jiffies + msecs_to_jiffies(500);
        dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);

diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 57332e3768e4d8eab0eebc64f12c3c6fde456eff..48fb264065db3218ef43f7fe4cdfe7f2245ae84d 100644 (file)
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -191,6 +191,19 @@
 #define DWC3_GHWPARAMS1_PWROPT(n)      ((n) << 24)
 #define DWC3_GHWPARAMS1_PWROPT_MASK    DWC3_GHWPARAMS1_PWROPT(3)
 
+/* Global HWPARAMS3 Register */
+#define DWC3_GHWPARAMS3_SSPHY_IFC(n)           ((n) & 3)
+#define DWC3_GHWPARAMS3_SSPHY_IFC_DIS          0
+#define DWC3_GHWPARAMS3_SSPHY_IFC_ENA          1
+#define DWC3_GHWPARAMS3_HSPHY_IFC(n)           (((n) & (3 << 2)) >> 2)
+#define DWC3_GHWPARAMS3_HSPHY_IFC_DIS          0
+#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI         1
+#define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI         2
+#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI    3
+#define DWC3_GHWPARAMS3_FSPHY_IFC(n)           (((n) & (3 << 4)) >> 4)
+#define DWC3_GHWPARAMS3_FSPHY_IFC_DIS          0
+#define DWC3_GHWPARAMS3_FSPHY_IFC_ENA          1
+
 /* Global HWPARAMS4 Register */
 #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n)   (((n) & (0x0f << 13)) >> 13)
 #define DWC3_MAX_HIBER_SCRATCHBUFS             15