#undef DUMPREG
 }
 
-static void _dispc_mgr_set_pol_freq(enum omap_channel channel, bool onoff,
-               bool rf, bool ieo, bool ipc, bool ihs, bool ivs)
-{
-       u32 l = 0;
-
-       DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d\n",
-                       onoff, rf, ieo, ipc, ihs, ivs);
-
-       l |= FLD_VAL(onoff, 17, 17);
-       l |= FLD_VAL(rf, 16, 16);
-       l |= FLD_VAL(ieo, 15, 15);
-       l |= FLD_VAL(ipc, 14, 14);
-       l |= FLD_VAL(ihs, 13, 13);
-       l |= FLD_VAL(ivs, 12, 12);
-
-       dispc_write_reg(DISPC_POL_FREQ(channel), l);
-}
-
-void dispc_mgr_set_pol_freq(enum omap_channel channel,
-               enum omap_panel_config config)
-{
-       _dispc_mgr_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
-                       (config & OMAP_DSS_LCD_RF) != 0,
-                       (config & OMAP_DSS_LCD_IEO) != 0,
-                       (config & OMAP_DSS_LCD_IPC) != 0,
-                       (config & OMAP_DSS_LCD_IHS) != 0,
-                       (config & OMAP_DSS_LCD_IVS) != 0);
-}
-
 /* with fck as input clock rate, find dispc dividers that produce req_pck */
 void dispc_find_clk_divs(unsigned long req_pck, unsigned long fck,
                struct dispc_clock_info *cinfo)
 
 void dispc_mgr_set_lcd_type_tft(enum omap_channel channel);
 void dispc_mgr_set_timings(enum omap_channel channel,
                struct omap_video_timings *timings);
-void dispc_mgr_set_pol_freq(enum omap_channel channel,
-               enum omap_panel_config config);
 unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
 unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
 unsigned long dispc_core_clk_rate(void);