drm/i915/xe2hpd: Configure CHICKEN_MISC_2 before enabling planes

Add step 9 from initialize display sequence.

v2: Commit subject improved

Bpsec: 49189
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-11-radhakrishna.sripada@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 03dc7edcc4430f69d6bb407127506c6234c5c224..a860d88a65da1dec4609b251fe6da04f1aeb0dbc 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1688,6 +1688,10 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
        if (IS_DG2(dev_priv))
                intel_snps_phy_wait_for_calibration(dev_priv);
 
+       /* 9. XE2_HPD: Program CHICKEN_MISC_2 before any cursor or planes are enabled */
+       if (DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 1))
+               intel_de_rmw(dev_priv, CHICKEN_MISC_2, BMG_DARB_HALF_BLK_END_BURST, 1);
+
        if (resume)
                intel_dmc_load_program(dev_priv);
 

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e22a82a5ddd75d8582482dffe66248a59b552c3f..ae692f461982eb9a2820bfe752dea347d10a6692 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3449,6 +3449,7 @@
 
 #define CHICKEN_MISC_2         _MMIO(0x42084)
 #define   CHICKEN_MISC_DISABLE_DPT     REG_BIT(30) /* adl,dg2 */
+#define   BMG_DARB_HALF_BLK_END_BURST  REG_BIT(27)
 #define   KBL_ARB_FILL_SPARE_14                REG_BIT(14)
 #define   KBL_ARB_FILL_SPARE_13                REG_BIT(13)
 #define   GLK_CL2_PWR_DOWN             REG_BIT(12)