arm64: dts: nuvoton: ma35d1: Add pinctrl and gpio nodes

Added the pinctrl node and its subnodes, the gpioa through gpion
nodes, to the MA35D1 device tree.

Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
Link: https://lore.kernel.org/r/20240819035647.306-3-ychuang570808@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
index a6b34e3e8b1093aafb70f61f3e24ba3168d516d4..e51b98f5bdce4c6594c48375aaf04a54b0582bac 100644 (file)
--- a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
+++ b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
@@ -95,6 +95,155 @@
                        clocks = <&clk_hxt>;
                };
 
+               pinctrl: pinctrl@40040000 {
+                       compatible = "nuvoton,ma35d1-pinctrl";
+                       reg = <0x0 0x40040000 0x0 0xc00>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       nuvoton,sys = <&sys>;
+                       ranges = <0x0 0x0 0x40040000 0x400>;
+
+                       gpioa: gpio@0 {
+                               reg = <0x0 0x40>;
+                               interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk GPA_GATE>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                       };
+
+                       gpiob: gpio@40 {
+                               reg = <0x40 0x40>;
+                               interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk GPB_GATE>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                       };
+
+                       gpioc: gpio@80 {
+                               reg = <0x80 0x40>;
+                               interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk GPC_GATE>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                       };
+
+                       gpiod: gpio@c0 {
+                               reg = <0xc0 0x40>;
+                               interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk GPD_GATE>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                       };
+
+                       gpioe: gpio@100 {
+                               reg = <0x100 0x40>;
+                               interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk GPE_GATE>;
+                               #gpio-cells = <2>;
+                               gpio-controller;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                       };
+
+                       gpiof: gpio@140 {
+                               reg = <0x140 0x40>;
+                               interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk GPF_GATE>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                       };
+
+                       gpiog: gpio@180 {
+                               reg = <0x180 0x40>;
+                               interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk GPG_GATE>;
+                               #gpio-cells = <2>;
+                               gpio-controller;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                       };
+
+                       gpioh: gpio@1c0 {
+                               reg = <0x1c0 0x40>;
+                               interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk GPH_GATE>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                       };
+
+                       gpioi: gpio@200 {
+                               reg = <0x200 0x40>;
+                               interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk GPI_GATE>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                       };
+
+                       gpioj: gpio@240 {
+                               reg = <0x240 0x40>;
+                               interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk GPJ_GATE>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                       };
+
+                       gpiok: gpio@280 {
+                               reg = <0x280 0x40>;
+                               interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk GPK_GATE>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                       };
+
+                       gpiol: gpio@2c0 {
+                               reg = <0x2c0 0x40>;
+                               interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk GPL_GATE>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                       };
+
+                       gpiom: gpio@300 {
+                               reg = <0x300 0x40>;
+                               interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk GPM_GATE>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                       };
+
+                       gpion: gpio@340 {
+                               reg = <0x340 0x40>;
+                               interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk GPN_GATE>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                       };
+               };
+
                uart0: serial@40700000 {
                        compatible = "nuvoton,ma35d1-uart";
                        reg = <0x0 0x40700000 0x0 0x100>;