extern int machine_check_e200(struct pt_regs *regs);
 extern int machine_check_47x(struct pt_regs *regs);
 int machine_check_8xx(struct pt_regs *regs);
+int machine_check_83xx(struct pt_regs *regs);
 
 extern void cpu_down_flush_e500v2(void);
 extern void cpu_down_flush_e500mc(void);
 
 #define   SRR1_PROGTRAP                0x00020000 /* Trap */
 #define   SRR1_PROGADDR                0x00010000 /* SRR0 contains subsequent addr */
 
+#define   SRR1_MCE_MCP         0x00080000 /* Machine check signal caused interrupt */
+
 #define SPRN_HSRR0     0x13A   /* Save/Restore Register 0 */
 #define SPRN_HSRR1     0x13B   /* Save/Restore Register 1 */
 #define   HSRR1_DENORM         0x00100000 /* Denorm exception */
 
                .machine_check          = machine_check_generic,
                .platform               = "ppc603",
        },
+#ifdef CONFIG_PPC_83xx
        {       /* e300c1 (a 603e core, plus some) on 83xx */
                .pvr_mask               = 0x7fff0000,
                .pvr_value              = 0x00830000,
                .icache_bsize           = 32,
                .dcache_bsize           = 32,
                .cpu_setup              = __setup_cpu_603,
-               .machine_check          = machine_check_generic,
+               .machine_check          = machine_check_83xx,
                .platform               = "ppc603",
        },
        {       /* e300c2 (an e300c1 core, plus some, minus FPU) on 83xx */
                .icache_bsize           = 32,
                .dcache_bsize           = 32,
                .cpu_setup              = __setup_cpu_603,
-               .machine_check          = machine_check_generic,
+               .machine_check          = machine_check_83xx,
                .platform               = "ppc603",
        },
        {       /* e300c3 (e300c1, plus one IU, half cache size) on 83xx */
                .icache_bsize           = 32,
                .dcache_bsize           = 32,
                .cpu_setup              = __setup_cpu_603,
-               .machine_check          = machine_check_generic,
+               .machine_check          = machine_check_83xx,
                .num_pmcs               = 4,
                .oprofile_cpu_type      = "ppc/e300",
                .oprofile_type          = PPC_OPROFILE_FSL_EMB,
                .icache_bsize           = 32,
                .dcache_bsize           = 32,
                .cpu_setup              = __setup_cpu_603,
-               .machine_check          = machine_check_generic,
+               .machine_check          = machine_check_83xx,
                .num_pmcs               = 4,
                .oprofile_cpu_type      = "ppc/e300",
                .oprofile_type          = PPC_OPROFILE_FSL_EMB,
                .platform               = "ppc603",
        },
+#endif
        {       /* default match, we assume split I/D cache & TB (non-601)... */
                .pvr_mask               = 0x00000000,
                .pvr_value              = 0x00000000,
 
 #include <linux/of_platform.h>
 #include <linux/pci.h>
 
+#include <asm/debug.h>
 #include <asm/io.h>
 #include <asm/hw_irq.h>
 #include <asm/ipic.h>
 
        mpc83xx_setup_pci();
 }
+
+int machine_check_83xx(struct pt_regs *regs)
+{
+       u32 mask = 1 << (31 - IPIC_MCP_WDT);
+
+       if (!(regs->msr & SRR1_MCE_MCP) || !(ipic_get_mcp_status() & mask))
+               return machine_check_generic(regs);
+       ipic_clear_mcp_status(mask);
+
+       if (debugger_fault_handler(regs))
+               return 1;
+
+       die("Watchdog NMI Reset", regs, 0);
+
+       return 1;
+}