mmc: sdhci-esdhc-imx: explicitly reset tuning circuit via RSTT bit

According to the i.MX Reference Manual, the RSTT bit (SYS_CTRL[28]) is
designed to reset the tuning circuit. While the Reference Manual states
that clearing EXECUTE_TUNING bit from 1 to 0 in AUTOCMD12_ERR_STATUS
can also set RSTT, this mechanism only works when the original
EXECUTE_TUNING bit was 1. When the bit is already 0, the tuning circuit
reset will not be triggered.

This explicit reset approach strengthens the tuning reliability and
aligns with the Reference Manual recommendations.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Luke Wang <ziniu.wang_1@nxp.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/20250409075550.3413032-2-ziniu.wang_1@nxp.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index 2f5c92d983e1a1cc7c0a4f6b6b2fa2989a5a5b4a..067f485987a6af2bda2735b0a578c7348fe7d204 100644 (file)
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -32,6 +32,7 @@
 
 #define ESDHC_SYS_CTRL_DTOCV_MASK      GENMASK(19, 16)
 #define ESDHC_SYS_CTRL_IPP_RST_N       BIT(23)
+#define ESDHC_SYS_CTRL_RESET_TUNING    BIT(28)
 #define        ESDHC_CTRL_D3CD                 0x08
 #define ESDHC_BURST_LEN_EN_INCR                (1 << 27)
 /* VENDOR SPEC register */
@@ -1065,7 +1066,7 @@ static void esdhc_reset_tuning(struct sdhci_host *host)
 {
        struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
        struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
-       u32 ctrl, tuning_ctrl;
+       u32 ctrl, tuning_ctrl, sys_ctrl;
        int ret;
 
        /* Reset the tuning circuit */
@@ -1089,6 +1090,11 @@ static void esdhc_reset_tuning(struct sdhci_host *host)
                                writel(tuning_ctrl, host->ioaddr + ESDHC_TUNING_CTRL);
                        }
 
+                       /* set the reset tuning bit */
+                       sys_ctrl = readl(host->ioaddr + ESDHC_SYSTEM_CONTROL);
+                       sys_ctrl |= ESDHC_SYS_CTRL_RESET_TUNING;
+                       writel(sys_ctrl, host->ioaddr + ESDHC_SYSTEM_CONTROL);
+
                        ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
                        ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
                        ctrl &= ~ESDHC_MIX_CTRL_EXE_TUNE;