phy: qcom-qmp-ufs: Move HS Rate B register setting to tbls_hs_b

Since now there is support for configuring the HS Rate B mode properly,
let's move the register setting to tbls_hs_b struct for all SoCs.

This allows the PHY to be configured in Rate A initially and then in
Rate B if requested by the UFS driver.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20230114071009.88102-7-manivannan.sadhasivam@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index bb329cfbb96ddc154a4be0a8fd36ce6ae1711513..a7261744f97161c9aec669a86fa6fa079b1f1ef3 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -219,8 +219,9 @@ static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes[] = {
        QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
+};
 
-       /* Rate B */
+static const struct qmp_phy_init_tbl sm6115_ufsphy_hs_b_serdes[] = {
        QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
 };
 
@@ -296,8 +297,9 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes[] = {
        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
+};
 
-       /* Rate B */
+static const struct qmp_phy_init_tbl sdm845_ufsphy_hs_b_serdes[] = {
        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
 };
 
@@ -362,8 +364,9 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes[] = {
        QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
        QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
+};
 
-       /* Rate B */
+static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_b_serdes[] = {
        QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
 };
 
@@ -411,7 +414,6 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] = {
        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
        QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
-
 };
 
 static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] = {
@@ -449,8 +451,9 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] = {
        QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
        QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
        QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
+};
 
-       /* Rate B */
+static const struct qmp_phy_init_tbl sm8350_ufsphy_hs_b_serdes[] = {
        QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
 };
 
@@ -684,6 +687,10 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
                .pcs            = sm8350_ufsphy_pcs,
                .pcs_num        = ARRAY_SIZE(sm8350_ufsphy_pcs),
        },
+       .tbls_hs_b = {
+               .serdes         = sm8350_ufsphy_hs_b_serdes,
+               .serdes_num     = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
+       },
        .clk_list               = sdm845_ufs_phy_clk_l,
        .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
        .vreg_list              = qmp_phy_vreg_l,
@@ -704,6 +711,10 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
                .pcs            = sdm845_ufsphy_pcs,
                .pcs_num        = ARRAY_SIZE(sdm845_ufsphy_pcs),
        },
+       .tbls_hs_b = {
+               .serdes         = sdm845_ufsphy_hs_b_serdes,
+               .serdes_num     = ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes),
+       },
        .clk_list               = sdm845_ufs_phy_clk_l,
        .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
        .vreg_list              = qmp_phy_vreg_l,
@@ -728,6 +739,10 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
                .pcs            = sm6115_ufsphy_pcs,
                .pcs_num        = ARRAY_SIZE(sm6115_ufsphy_pcs),
        },
+       .tbls_hs_b = {
+               .serdes         = sm6115_ufsphy_hs_b_serdes,
+               .serdes_num     = ARRAY_SIZE(sm6115_ufsphy_hs_b_serdes),
+       },
        .clk_list               = sdm845_ufs_phy_clk_l,
        .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
        .vreg_list              = qmp_phy_vreg_l,
@@ -750,6 +765,10 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
                .pcs            = sm8150_ufsphy_pcs,
                .pcs_num        = ARRAY_SIZE(sm8150_ufsphy_pcs),
        },
+       .tbls_hs_b = {
+               .serdes         = sm8150_ufsphy_hs_b_serdes,
+               .serdes_num     = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
+       },
        .clk_list               = sdm845_ufs_phy_clk_l,
        .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
        .vreg_list              = qmp_phy_vreg_l,
@@ -770,6 +789,10 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
                .pcs            = sm8350_ufsphy_pcs,
                .pcs_num        = ARRAY_SIZE(sm8350_ufsphy_pcs),
        },
+       .tbls_hs_b = {
+               .serdes         = sm8350_ufsphy_hs_b_serdes,
+               .serdes_num     = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
+       },
        .clk_list               = sdm845_ufs_phy_clk_l,
        .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
        .vreg_list              = qmp_phy_vreg_l,
@@ -790,6 +813,10 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
                .pcs            = sm8350_ufsphy_pcs,
                .pcs_num        = ARRAY_SIZE(sm8350_ufsphy_pcs),
        },
+       .tbls_hs_b = {
+               .serdes         = sm8350_ufsphy_hs_b_serdes,
+               .serdes_num     = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
+       },
        .clk_list               = sm8450_ufs_phy_clk_l,
        .num_clks               = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
        .vreg_list              = qmp_phy_vreg_l,