x86/speculation: Clean up retpoline code in bugs.c

Now that the minimal retpoline modes are removed, also remove
unnecessary checks to simplify retpoline code.

Orabug: 29211617

Signed-off-by: Alejandro Jimenez <alejandro.j.jimenez@oracle.com>
Reviewed-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Signed-off-by: Brian Maly <brian.maly@oracle.com>

diff --git a/arch/x86/kernel/cpu/bugs_64.c b/arch/x86/kernel/cpu/bugs_64.c
index a4c824ce0994e4fa2298775e1b43aabd1ae2de8f..e5251bfc606e4d8f645cadfa01695b79421f438b 100644 (file)
--- a/arch/x86/kernel/cpu/bugs_64.c
+++ b/arch/x86/kernel/cpu/bugs_64.c
@@ -457,26 +457,22 @@ static void retpoline_init(void)
        setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
 
        if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
-               if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
-                       pr_err("Spectre mitigation: LFENCE not serializing, setting up generic retpoline\n");
-               else
+               if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
                        setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD);
+                       retpoline_mode = SPECTRE_V2_RETPOLINE_AMD;
+                       return;
+               }
+               pr_err("Spectre mitigation: LFENCE not serializing, setting up generic retpoline\n");
        }
 
-       if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
-           boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
-               retpoline_mode = SPECTRE_V2_RETPOLINE_AMD;
-       else
-               retpoline_mode = SPECTRE_V2_RETPOLINE_GENERIC;
+       retpoline_mode = SPECTRE_V2_RETPOLINE_GENERIC;
 }
 
 static void __init retpoline_activate(enum spectre_v2_mitigation mode)
 {
        retpoline_enable();
        /* IBRS is unnecessary with retpoline mitigation. */
-       if (mode == SPECTRE_V2_RETPOLINE_GENERIC ||
-               mode == SPECTRE_V2_RETPOLINE_AMD)
-               disable_ibrs_and_friends(false);
+       disable_ibrs_and_friends(false);
 }
 
 static void spec_ctrl_flush_all_cpus(u32 msr_nr, u64 val)