x86/cpu: Update init data for new Airmont CPU model

Update properties for newly added Airmont CPU variant.

Signed-off-by: Rahul Tanwar <rahul.tanwar@linux.intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Cc: Gayatri Kammela <gayatri.kammela@intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/20190905193020.14707-5-tony.luck@intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>

diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index b6a9e27755d743637d82714f8e2885c4a01be637..030e52749a74093658064e6f21bcc6df934e13fe 100644 (file)
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -1059,6 +1059,7 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
        VULNWL_INTEL(CORE_YONAH,                NO_SSB),
 
        VULNWL_INTEL(ATOM_AIRMONT_MID,          NO_L1TF | MSBDS_ONLY | NO_SWAPGS),
+       VULNWL_INTEL(ATOM_AIRMONT_NP,           NO_L1TF | NO_SWAPGS),
 
        VULNWL_INTEL(ATOM_GOLDMONT,             NO_MDS | NO_L1TF | NO_SWAPGS),
        VULNWL_INTEL(ATOM_GOLDMONT_D,           NO_MDS | NO_L1TF | NO_SWAPGS),

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index e2082ccccf130c7498496f31403dcc3225bf1a87..c2fdc00df1633f6d846ae96353045ec1dc71f8eb 100644 (file)
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -268,6 +268,7 @@ static void early_init_intel(struct cpuinfo_x86 *c)
                case INTEL_FAM6_ATOM_SALTWELL_MID:
                case INTEL_FAM6_ATOM_SALTWELL_TABLET:
                case INTEL_FAM6_ATOM_SILVERMONT_MID:
+               case INTEL_FAM6_ATOM_AIRMONT_NP:
                        set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
                        break;
                default:

diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c
index 067858fe4db8fcf5063dcf0952cfb90add3e59de..e0cbe4f2af493deef46199b1712c2f95d472a18a 100644 (file)
--- a/arch/x86/kernel/tsc_msr.c
+++ b/arch/x86/kernel/tsc_msr.c
@@ -58,6 +58,10 @@ static const struct freq_desc freq_desc_ann = {
        1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0 }
 };
 
+static const struct freq_desc freq_desc_lgm = {
+       1, { 78000, 78000, 78000, 78000, 78000, 78000, 78000, 78000 }
+};
+
 static const struct x86_cpu_id tsc_msr_cpu_ids[] = {
        INTEL_CPU_FAM6(ATOM_SALTWELL_MID,       freq_desc_pnw),
        INTEL_CPU_FAM6(ATOM_SALTWELL_TABLET,    freq_desc_clv),
@@ -65,6 +69,7 @@ static const struct x86_cpu_id tsc_msr_cpu_ids[] = {
        INTEL_CPU_FAM6(ATOM_SILVERMONT_MID,     freq_desc_tng),
        INTEL_CPU_FAM6(ATOM_AIRMONT,            freq_desc_cht),
        INTEL_CPU_FAM6(ATOM_AIRMONT_MID,        freq_desc_ann),
+       INTEL_CPU_FAM6(ATOM_AIRMONT_NP,         freq_desc_lgm),
        {}
 };