KVM: selftests: Verify the guest can read back the x2APIC ICR it wrote

Now that the BUSY bit mess is gone (for x2APIC), verify that the *guest*
can read back the ICR value that it wrote.  Due to the divergent
behavior between AMD and Intel with respect to the backing storage of the
ICR in the vAPIC page, emulating a seemingly simple MSR write is quite
complex.

Link: https://lore.kernel.org/r/20240719235107.3023592-10-seanjc@google.com
Signed-off-by: Sean Christopherson <seanjc@google.com>

diff --git a/tools/testing/selftests/kvm/x86_64/xapic_state_test.c b/tools/testing/selftests/kvm/x86_64/xapic_state_test.c
index a17b75fb250648f8bc264b3351f0903e365858f5..dbd4f23ce92e8681fbc406a500b913ea4c354562 100644 (file)
--- a/tools/testing/selftests/kvm/x86_64/xapic_state_test.c
+++ b/tools/testing/selftests/kvm/x86_64/xapic_state_test.c
@@ -45,10 +45,12 @@ static void x2apic_guest_code(void)
                uint64_t val = x2apic_read_reg(APIC_IRR) |
                               x2apic_read_reg(APIC_IRR + 0x10) << 32;
 
-               if (val & X2APIC_RSVD_BITS_MASK)
+               if (val & X2APIC_RSVD_BITS_MASK) {
                        x2apic_write_reg_fault(APIC_ICR, val);
-               else
+               } else {
                        x2apic_write_reg(APIC_ICR, val);
+                       GUEST_ASSERT_EQ(x2apic_read_reg(APIC_ICR), val);
+               }
                GUEST_SYNC(val);
        } while (1);
 }