drm/msm/dpu: clean up SRC addresses when setting up SSPP for solid fill

Set SSPP_SRCn_ADDR registers to 0 while setting up solid fill, as we can
not be sure that the previous address is still valid.

Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Tested-by: Abhinav Kumar <quic_abhinavk@quicinc.com> # sc7280
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/527324/
Link: https://lore.kernel.org/r/20230316161653.4106395-11-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index 3030cd3b253ae2c7644c885cc37851eefa3d80f6..0a43c5682b2bc8eaf98ad49a9bcb0e9ebde1b415 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -563,11 +563,16 @@ static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
 static void dpu_hw_sspp_setup_solidfill(struct dpu_sw_pipe *pipe, u32 color)
 {
        struct dpu_hw_sspp *ctx = pipe->sspp;
+       struct dpu_hw_sspp_cfg cfg;
        u32 idx;
 
        if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx))
                return;
 
+       /* cleanup source addresses */
+       memset(&cfg, 0, sizeof(cfg));
+       ctx->ops.setup_sourceaddress(pipe, &cfg);
+
        if (pipe->multirect_index == DPU_SSPP_RECT_SOLO ||
            pipe->multirect_index == DPU_SSPP_RECT_0)
                DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR + idx, color);