clk: tegra: Don't enable PLLE HW sequencer at init

PLLE hardware power sequencer references PEX/SATA UPHY PLL hardware
power sequencers' output to enable/disable PLLE. PLLE hardware power
sequencer has to be enabled only after PEX/SATA UPHY PLL's sequencers
are enabled.

Signed-off-by: JC Kuo <jckuo@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index c5cc0a2dac6ff880de18824553701c9d06c5ee5e..0193cebe8c5a3e21abe35032ace7314e10e7b103 100644 (file)
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -2515,18 +2515,6 @@ static int clk_plle_tegra210_enable(struct clk_hw *hw)
        pll_writel(val, PLLE_SS_CTRL, pll);
        udelay(1);
 
-       val = pll_readl_misc(pll);
-       val &= ~PLLE_MISC_IDDQ_SW_CTRL;
-       pll_writel_misc(val, pll);
-
-       val = pll_readl(pll->params->aux_reg, pll);
-       val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SS_SEQ_INCLUDE);
-       val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
-       pll_writel(val, pll->params->aux_reg, pll);
-       udelay(1);
-       val |= PLLE_AUX_SEQ_ENABLE;
-       pll_writel(val, pll->params->aux_reg, pll);
-
 out:
        if (pll->lock)
                spin_unlock_irqrestore(pll->lock, flags);