scsi: mpt3sas: Increased/Additional MSIX support for SAS35 devices.

For SAS35 devices MSIX vectors are inceased to 128 from 96. To support this
Reply post host index register count is increased to 16. Also variable
msix96_vector is replaced with combined_reply_queue and variable
combined_reply_index_count is added to set different values for SAS3 and
SAS35 devices.

Signed-off-by: Chaitra P B <chaitra.basappa@broadcom.com>
Signed-off-by: Sathya Prakash <sathya.prakash@broadcom.com>
Signed-off-by: Suganath Prabu S <suganath-prabu.subramani@broadcom.com>
Reviewed-by: Hannes Reinecke <hare@suse.com>
Reviewed-by: Tomas Henzl <thenzl@redhat.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>

diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c b/drivers/scsi/mpt3sas/mpt3sas_base.c
index 9ad7f7ceced8fe18c5bfd46a014f934449d01894..43cdc02e6a0411f19184b8dd16961f23e00d2b22 100644 (file)
--- a/drivers/scsi/mpt3sas/mpt3sas_base.c
+++ b/drivers/scsi/mpt3sas/mpt3sas_base.c
@@ -1078,7 +1078,7 @@ _base_interrupt(int irq, void *bus_id)
         * new reply host index value in ReplyPostIndex Field and msix_index
         * value in MSIxIndex field.
         */
-       if (ioc->msix96_vector)
+       if (ioc->combined_reply_queue)
                writel(reply_q->reply_post_host_index | ((msix_index  & 7) <<
                        MPI2_RPHI_MSIX_INDEX_SHIFT),
                        ioc->replyPostRegisterIndex[msix_index/8]);
@@ -2052,7 +2052,7 @@ mpt3sas_base_unmap_resources(struct MPT3SAS_ADAPTER *ioc)
        _base_free_irq(ioc);
        _base_disable_msix(ioc);
 
-       if (ioc->msix96_vector) {
+       if (ioc->combined_reply_queue) {
                kfree(ioc->replyPostRegisterIndex);
                ioc->replyPostRegisterIndex = NULL;
        }
@@ -2162,7 +2162,7 @@ mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc)
        /* Use the Combined reply queue feature only for SAS3 C0 & higher
         * revision HBAs and also only when reply queue count is greater than 8
         */
-       if (ioc->msix96_vector && ioc->reply_queue_count > 8) {
+       if (ioc->combined_reply_queue && ioc->reply_queue_count > 8) {
                /* Determine the Supplemental Reply Post Host Index Registers
                 * Addresse. Supplemental Reply Post Host Index Registers
                 * starts at offset MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET and
@@ -2170,7 +2170,7 @@ mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc)
                 * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET from previous one.
                 */
                ioc->replyPostRegisterIndex = kcalloc(
-                    MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT,
+                    ioc->combined_reply_index_count,
                     sizeof(resource_size_t *), GFP_KERNEL);
                if (!ioc->replyPostRegisterIndex) {
                        dfailprintk(ioc, printk(MPT3SAS_FMT
@@ -2180,14 +2180,14 @@ mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc)
                        goto out_fail;
                }
 
-               for (i = 0; i < MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT; i++) {
+               for (i = 0; i < ioc->combined_reply_index_count; i++) {
                        ioc->replyPostRegisterIndex[i] = (resource_size_t *)
                             ((u8 *)&ioc->chip->Doorbell +
                             MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET +
                             (i * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET));
                }
        } else
-               ioc->msix96_vector = 0;
+               ioc->combined_reply_queue = 0;
 
        if (ioc->is_warpdrive) {
                ioc->reply_post_host_index[0] = (resource_size_t __iomem *)
@@ -5140,7 +5140,7 @@ _base_make_ioc_operational(struct MPT3SAS_ADAPTER *ioc)
 
        /* initialize reply post host index */
        list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
-               if (ioc->msix96_vector)
+               if (ioc->combined_reply_queue)
                        writel((reply_q->msix_index & 7)<<
                           MPI2_RPHI_MSIX_INDEX_SHIFT,
                           ioc->replyPostRegisterIndex[reply_q->msix_index/8]);

diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.h b/drivers/scsi/mpt3sas/mpt3sas_base.h
index 3d75c57215b3968991d3516bc47ff4b4d5e6b889..acb41062867177f22dfd087057dfed2c491bd11e 100644 (file)
--- a/drivers/scsi/mpt3sas/mpt3sas_base.h
+++ b/drivers/scsi/mpt3sas/mpt3sas_base.h
@@ -300,8 +300,9 @@
  * There are twelve Supplemental Reply Post Host Index Registers
  * and each register is at offset 0x10 bytes from the previous one.
  */
-#define MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT 12
-#define MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET (0x10)
+#define MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT_G3    12
+#define MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT_G35   16
+#define MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET      (0x10)
 
 /* OEM Identifiers */
 #define MFG10_OEM_ID_INVALID                   (0x00000000)
@@ -1158,7 +1159,8 @@ struct MPT3SAS_ADAPTER {
        u8              reply_queue_count;
        struct list_head reply_queue_list;
 
-       u8              msix96_vector;
+       u8              combined_reply_queue;
+       u8              combined_reply_index_count;
        /* reply post register index */
        resource_size_t **replyPostRegisterIndex;
 

diff --git a/drivers/scsi/mpt3sas/mpt3sas_scsih.c b/drivers/scsi/mpt3sas/mpt3sas_scsih.c
index 521849d5d59817f4e66d3fc85e67e2d7448e1914..a1c541d9e550d6ee46d64aaf310b105e68e4d740 100644 (file)
--- a/drivers/scsi/mpt3sas/mpt3sas_scsih.c
+++ b/drivers/scsi/mpt3sas/mpt3sas_scsih.c
@@ -8748,8 +8748,15 @@ _scsih_probe(struct pci_dev *pdev, const struct pci_device_id *id)
                }
                if ((ioc->hba_mpi_version_belonged == MPI25_VERSION &&
                        pdev->revision >= SAS3_PCI_DEVICE_C0_REVISION) ||
-                       (ioc->hba_mpi_version_belonged == MPI26_VERSION))
-                       ioc->msix96_vector = 1;
+                       (ioc->hba_mpi_version_belonged == MPI26_VERSION)) {
+                       ioc->combined_reply_queue = 1;
+                       if (ioc->is_gen35_ioc)
+                               ioc->combined_reply_index_count =
+                                MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT_G35;
+                       else
+                               ioc->combined_reply_index_count =
+                                MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT_G3;
+               }
                break;
        default:
                return -ENODEV;