OMAP: DSS2: DSI: Fix DSI PLL power bug

OMAP3630 has a HW bug causing DSI PLL power command POWER_ON_DIV (0x3)
to not work properly. The bug prevents us from enabling DSI PLL power
only to HS divider block.

This patch adds a dss feature for the bug and converts POWER_ON_DIV
requests to POWER_ON_ALL (0x2).

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>

diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
index 1464ac4f6f58918400c680a66f087a650637138f..cbd9ca48d6ecef175e1c5204956ba3fbb7915974 100644 (file)
--- a/drivers/video/omap2/dss/dsi.c
+++ b/drivers/video/omap2/dss/dsi.c
@@ -1059,6 +1059,11 @@ static int dsi_pll_power(enum dsi_pll_power_state state)
 {
        int t = 0;
 
+       /* DSI-PLL power command 0x3 is not working */
+       if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) &&
+                       state == DSI_PLL_POWER_ON_DIV)
+               state = DSI_PLL_POWER_ON_ALL;
+
        REG_FLD_MOD(DSI_CLK_CTRL, state, 31, 30);       /* PLL_PWR_CMD */
 
        /* PLL_PWR_STATUS */

diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c
index aa1622241d0d728612c57bda460951d251cf590d..8c50e18bc0b0c8f90abe0a6b17ee23a1f6498b98 100644 (file)
--- a/drivers/video/omap2/dss/dss_features.c
+++ b/drivers/video/omap2/dss/dss_features.c
@@ -271,7 +271,7 @@ static struct omap_dss_features omap3630_dss_features = {
                FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE |
                FEAT_PRE_MULT_ALPHA | FEAT_FUNCGATED |
                FEAT_ROWREPEATENABLE | FEAT_LINEBUFFERSPLIT |
-               FEAT_RESIZECONF,
+               FEAT_RESIZECONF | FEAT_DSI_PLL_PWR_BUG,
 
        .num_mgrs = 2,
        .num_ovls = 3,

diff --git a/drivers/video/omap2/dss/dss_features.h b/drivers/video/omap2/dss/dss_features.h
index 12e9c4ef0dec4426fb0197c62559152f623ef703..37922ce6b8b190b6800037d3df068d847dd5f3d7 100644 (file)
--- a/drivers/video/omap2/dss/dss_features.h
+++ b/drivers/video/omap2/dss/dss_features.h
@@ -40,6 +40,8 @@ enum dss_feat_id {
        /* Independent core clk divider */
        FEAT_CORE_CLK_DIV       = 1 << 11,
        FEAT_LCD_CLK_SRC        = 1 << 12,
+       /* DSI-PLL power command 0x3 is not working */
+       FEAT_DSI_PLL_PWR_BUG    = 1 << 13,
 };
 
 /* DSS register field id */