drm/i915: pass dev_priv explicitly to PIPE_LINK_N1

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_LINK_N1 register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/0960c3726a36999b38084dce6c3824882921c475.1717514638.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a3249d782a8b4538ccb64c571d245928bc6afc46..eef3179845649a52bcec7ad443ed430f0a67a54f 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2644,7 +2644,7 @@ void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
                              PIPE_DATA_M1(dev_priv, transcoder),
                              PIPE_DATA_N1(dev_priv, transcoder),
                              PIPE_LINK_M1(dev_priv, transcoder),
-                             PIPE_LINK_N1(transcoder));
+                             PIPE_LINK_N1(dev_priv, transcoder));
        else
                intel_set_m_n(dev_priv, m_n,
                              PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
@@ -3343,7 +3343,7 @@ void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
                              PIPE_DATA_M1(dev_priv, transcoder),
                              PIPE_DATA_N1(dev_priv, transcoder),
                              PIPE_LINK_M1(dev_priv, transcoder),
-                             PIPE_LINK_N1(transcoder));
+                             PIPE_LINK_N1(dev_priv, transcoder));
        else
                intel_get_m_n(dev_priv, m_n,
                              PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),

diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
index eea956603cc81d67f55f8cae2e278a30fa270d21..95b4b76d3b45542f4b4cb365acd0a748daf6273a 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -265,7 +265,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
                vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e;
                vgpu_vreg_t(vgpu, PIPE_DATA_N1(dev_priv, TRANSCODER_A)) = 0x800000;
                vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A)) = 0x3cd6e;
-               vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
+               vgpu_vreg_t(vgpu, PIPE_LINK_N1(dev_priv, TRANSCODER_A)) = 0x80000;
 
                /* Enable per-DDI/PORT vreg */
                if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
@@ -399,7 +399,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
                vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e;
                vgpu_vreg_t(vgpu, PIPE_DATA_N1(dev_priv, TRANSCODER_A)) = 0x800000;
                vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A)) = 0x3cd6e;
-               vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
+               vgpu_vreg_t(vgpu, PIPE_LINK_N1(dev_priv, TRANSCODER_A)) = 0x80000;
        }
 
        if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index d0c4e555435a76c9a4f3b60f84f65f32270ccc92..7416068e7c825e09fa85c72dc0e7afab318fe490 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -673,7 +673,7 @@ static void vgpu_update_refresh_rate(struct intel_vgpu *vgpu)
 
        /* Get DP link symbol clock M/N */
        link_m = vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A));
-       link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A));
+       link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(dev_priv, TRANSCODER_A));
 
        /* Get H/V total from transcoder timing */
        htotal = (vgpu_vreg_t(vgpu, TRANS_HTOTAL(dev_priv, TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT);

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f45bb6d5705bc759290e359f7f567e8c53b5dc5d..86ca2798fd2c67aceaafb3b6dab3403d9f3f85c3 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2303,7 +2303,7 @@
 #define PIPE_DATA_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M2)
 #define PIPE_DATA_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2)
 #define PIPE_LINK_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1)
-#define PIPE_LINK_N1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1)
+#define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1)
 #define PIPE_LINK_M2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M2)
 #define PIPE_LINK_N2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N2)
 

diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index c08b8e75537762dc799d936fe89d27106456181d..00ce7147a9b6291c84cfdcbb9c427ebcc9ae3e01 100644 (file)
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -271,7 +271,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_A));
        MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_A));
        MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_A));
-       MMIO_D(PIPE_LINK_N1(TRANSCODER_A));
+       MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_A));
        MMIO_D(PIPE_LINK_M2(TRANSCODER_A));
        MMIO_D(PIPE_LINK_N2(TRANSCODER_A));
        MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_B));
@@ -279,7 +279,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_B));
        MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_B));
        MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_B));
-       MMIO_D(PIPE_LINK_N1(TRANSCODER_B));
+       MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_B));
        MMIO_D(PIPE_LINK_M2(TRANSCODER_B));
        MMIO_D(PIPE_LINK_N2(TRANSCODER_B));
        MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_C));
@@ -287,7 +287,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_C));
        MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_C));
        MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_C));
-       MMIO_D(PIPE_LINK_N1(TRANSCODER_C));
+       MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_C));
        MMIO_D(PIPE_LINK_M2(TRANSCODER_C));
        MMIO_D(PIPE_LINK_N2(TRANSCODER_C));
        MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_EDP));
@@ -295,7 +295,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_EDP));
        MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_EDP));
        MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_EDP));
-       MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP));
+       MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_EDP));
        MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP));
        MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP));
        MMIO_D(PF_CTL(PIPE_A));