/* stage 2 */
                { 0x834a, 0x40 },
-               { 0x831d, 0x10 },
 
                /* MK limit */
                { 0x832d, 0x38 },
                { 0x8325, 0x00 },
                { 0x832a, 0x01 },
                { 0x834a, 0x10 },
-               { 0x831d, 0x10 },
-               { 0x8326, 0x37 },
        };
+       u8 pol = 0x10;
 
-       regmap_multi_reg_write(lt9611->regmap, reg_cfg, ARRAY_SIZE(reg_cfg));
+       if (mode->flags & DRM_MODE_FLAG_NHSYNC)
+               pol |= 0x2;
+       if (mode->flags & DRM_MODE_FLAG_NVSYNC)
+               pol |= 0x1;
+       regmap_write(lt9611->regmap, 0x831d, pol);
+
+       if (mode->hdisplay == 3840)
+               regmap_multi_reg_write(lt9611->regmap, reg_cfg2, ARRAY_SIZE(reg_cfg2));
+       else
+               regmap_multi_reg_write(lt9611->regmap, reg_cfg, ARRAY_SIZE(reg_cfg));
 
        switch (mode->hdisplay) {
        case 640:
                regmap_write(lt9611->regmap, 0x8326, 0x37);
                break;
        case 3840:
-               regmap_multi_reg_write(lt9611->regmap, reg_cfg2, ARRAY_SIZE(reg_cfg2));
+               regmap_write(lt9611->regmap, 0x8326, 0x37);
                break;
        }