drm/i915: Pass crtc+cpu_transcoder to intel_cpu_transcoder_set_m_n()

Instead of passing in the whole crtc state let's pass in just
the bits of state we need. This will help with the DRRS code
which shouldn't really be accessing the atomic state stuff directly
as it gets called outside the normal atomic flows.

v2: Fix set_m1_n1 vs. set_m2_n2 fumble for i9xx (Jani)

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220128103757.22461-7-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index b02b327331f8dbb45686d964a73d6d2c5a30ce52..360f62665b54c71127fe3d2166217a02ef39a3fc 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2498,6 +2498,8 @@ static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
                                    const struct drm_connector_state *conn_state)
 {
        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+       struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+       enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 
        if (DISPLAY_VER(dev_priv) >= 12)
                tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
@@ -2510,9 +2512,9 @@ static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
        if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
                intel_ddi_set_dp_msa(crtc_state, conn_state);
 
-               intel_cpu_transcoder_set_m1_n1(crtc_state,
+               intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
                                               &crtc_state->dp_m_n);
-               intel_cpu_transcoder_set_m2_n2(crtc_state,
+               intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
                                               &crtc_state->dp_m2_n2);
        }
 }

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index cb5b89815163884b950aeabec5449354f0f6c694..8df7838e628d0505844b4224140d93aeb911ebe8 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -118,7 +118,7 @@
 
 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
-static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
+static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
                                         const struct intel_link_m_n *m_n);
 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
@@ -1816,6 +1816,7 @@ static void ilk_crtc_enable(struct intel_atomic_state *state,
        const struct intel_crtc_state *new_crtc_state =
                intel_atomic_get_new_crtc_state(state, crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+       enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
        enum pipe pipe = crtc->pipe;
 
        if (drm_WARN_ON(&dev_priv->drm, crtc->active))
@@ -1836,12 +1837,11 @@ static void ilk_crtc_enable(struct intel_atomic_state *state,
 
        if (intel_crtc_has_dp_encoder(new_crtc_state)) {
                if (new_crtc_state->has_pch_encoder) {
-                       intel_pch_transcoder_set_m_n(new_crtc_state,
-                                                    &new_crtc_state->dp_m_n);
+                       intel_pch_transcoder_set_m_n(crtc, &new_crtc_state->dp_m_n);
                } else {
-                       intel_cpu_transcoder_set_m1_n1(new_crtc_state,
+                       intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
                                                       &new_crtc_state->dp_m_n);
-                       intel_cpu_transcoder_set_m2_n2(new_crtc_state,
+                       intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
                                                       &new_crtc_state->dp_m2_n2);
                }
        }
@@ -1850,7 +1850,7 @@ static void ilk_crtc_enable(struct intel_atomic_state *state,
        intel_set_pipe_src_size(new_crtc_state);
 
        if (new_crtc_state->has_pch_encoder)
-               intel_cpu_transcoder_set_m1_n1(new_crtc_state,
+               intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
                                               &new_crtc_state->fdi_m_n);
 
        ilk_set_pipeconf(new_crtc_state);
@@ -2017,7 +2017,7 @@ static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta
                               crtc_state->pixel_multiplier - 1);
 
        if (crtc_state->has_pch_encoder)
-               intel_cpu_transcoder_set_m1_n1(crtc_state,
+               intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
                                               &crtc_state->fdi_m_n);
 
        hsw_set_frame_start_delay(crtc_state);
@@ -2452,15 +2452,16 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state,
        const struct intel_crtc_state *new_crtc_state =
                intel_atomic_get_new_crtc_state(state, crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+       enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
        enum pipe pipe = crtc->pipe;
 
        if (drm_WARN_ON(&dev_priv->drm, crtc->active))
                return;
 
        if (intel_crtc_has_dp_encoder(new_crtc_state)) {
-               intel_cpu_transcoder_set_m1_n1(new_crtc_state,
+               intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
                                               &new_crtc_state->dp_m_n);
-               intel_cpu_transcoder_set_m2_n2(new_crtc_state,
+               intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
                                               &new_crtc_state->dp_m2_n2);
        }
 
@@ -2508,15 +2509,16 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state,
        const struct intel_crtc_state *new_crtc_state =
                intel_atomic_get_new_crtc_state(state, crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+       enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
        enum pipe pipe = crtc->pipe;
 
        if (drm_WARN_ON(&dev_priv->drm, crtc->active))
                return;
 
        if (intel_crtc_has_dp_encoder(new_crtc_state)) {
-               intel_cpu_transcoder_set_m1_n1(new_crtc_state,
+               intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
                                               &new_crtc_state->dp_m_n);
-               intel_cpu_transcoder_set_m2_n2(new_crtc_state,
+               intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
                                               &new_crtc_state->dp_m2_n2);
        }
 
@@ -3140,10 +3142,9 @@ static void intel_set_m_n(struct drm_i915_private *i915,
        intel_de_write(i915, link_n_reg, m_n->link_n);
 }
 
-static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
+static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
                                         const struct intel_link_m_n *m_n)
 {
-       struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        enum pipe pipe = crtc->pipe;
 
@@ -3165,13 +3166,12 @@ static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
        return DISPLAY_VER(dev_priv) == 7 || IS_CHERRYVIEW(dev_priv);
 }
 
-void intel_cpu_transcoder_set_m1_n1(const struct intel_crtc_state *crtc_state,
+void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
+                                   enum transcoder transcoder,
                                    const struct intel_link_m_n *m_n)
 {
-       struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        enum pipe pipe = crtc->pipe;
-       enum transcoder transcoder = crtc_state->cpu_transcoder;
 
        if (DISPLAY_VER(dev_priv) >= 5)
                intel_set_m_n(dev_priv, m_n,
@@ -3183,12 +3183,11 @@ void intel_cpu_transcoder_set_m1_n1(const struct intel_crtc_state *crtc_state,
                              PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
 }
 
-void intel_cpu_transcoder_set_m2_n2(const struct intel_crtc_state *crtc_state,
+void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
+                                   enum transcoder transcoder,
                                    const struct intel_link_m_n *m_n)
 {
-       struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-       enum transcoder transcoder = crtc_state->cpu_transcoder;
 
        if (!transcoder_has_m2_n2(dev_priv, transcoder))
                return;

diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 9a232bdef0f29a1b730dc1b69b9d7ef78081c3d3..e8b41b67a366df0a0ba94ec3a6cf9d6d83549c3f 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -604,9 +604,11 @@ bool intel_fuzzy_clock_check(int clock1, int clock2);
 
 void intel_display_prepare_reset(struct drm_i915_private *dev_priv);
 void intel_display_finish_reset(struct drm_i915_private *dev_priv);
-void intel_cpu_transcoder_set_m1_n1(const struct intel_crtc_state *crtc_state,
+void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
+                                   enum transcoder cpu_transcoder,
                                    const struct intel_link_m_n *m_n);
-void intel_cpu_transcoder_set_m2_n2(const struct intel_crtc_state *crtc_state,
+void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
+                                   enum transcoder cpu_transcoder,
                                    const struct intel_link_m_n *m_n);
 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
                                    enum transcoder cpu_transcoder,

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 4e8d65fa608631e437287eb5b5b1a991b8f675e4..30edb9117443160a4a06882dd7866ebab3855354 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -473,6 +473,7 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
        struct intel_digital_port *dig_port = intel_mst->primary;
        struct intel_dp *intel_dp = &dig_port->dp;
        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+       struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
        struct intel_connector *connector =
                to_intel_connector(conn_state->connector);
        int ret;
@@ -523,7 +524,7 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
 
        intel_ddi_set_dp_msa(pipe_config, conn_state);
 
-       intel_cpu_transcoder_set_m1_n1(pipe_config,
+       intel_cpu_transcoder_set_m1_n1(crtc, pipe_config->cpu_transcoder,
                                       &pipe_config->dp_m_n);
 }
 

diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c
index a911066c7809c2ed9c421c2060a4221a267f5cc8..53f014b4436b5cbb2ad19720bd0305229d465c54 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_drrs.c
+++ b/drivers/gpu/drm/i915/display/intel_drrs.c
@@ -115,7 +115,10 @@ static void
 intel_drrs_set_refresh_rate_m_n(const struct intel_crtc_state *crtc_state,
                                enum drrs_refresh_rate_type refresh_type)
 {
-       intel_cpu_transcoder_set_m1_n1(crtc_state, refresh_type == DRRS_LOW_RR ?
+       struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+       intel_cpu_transcoder_set_m1_n1(crtc, crtc_state->cpu_transcoder,
+                                      refresh_type == DRRS_LOW_RR ?
                                       &crtc_state->dp_m2_n2 : &crtc_state->dp_m_n);
 }