drm/amdgpu: enable RAS support for sienna cichlid

enabled GECC error injection and query support

Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 89cb0ae9da9d4fd2e4f31521db9f6005f9436c92..1a55f6f492fdb1100c8b0824f03fe82fdba74c44 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -1965,8 +1965,9 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev,
        *supported = 0;
 
        if (amdgpu_sriov_vf(adev) || !adev->is_atom_fw ||
-           (adev->asic_type != CHIP_VEGA20 &&
-            adev->asic_type != CHIP_ARCTURUS))
+           (adev->asic_type != CHIP_VEGA20   &&
+            adev->asic_type != CHIP_ARCTURUS &&
+            adev->asic_type != CHIP_SIENNA_CICHLID))
                return;
 
        if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 35d21f330b0ab87995e373cc67b5f73c70915740..dd91a93de62aed4e63e13cc2c9ff21ae335b8f99 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -633,6 +633,10 @@ static int gmc_v10_0_late_init(void *handle)
        if (r)
                return r;
 
+       r = amdgpu_gmc_ras_late_init(adev);
+       if (r)
+               return r;
+
        return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
 }