printk("%saer_uncor_severity: 0x%08x\n",
                       pfx, aer->uncor_severity);
                printk("%sTLP Header: %08x %08x %08x %08x\n", pfx,
-                      aer->header_log.dw0, aer->header_log.dw1,
-                      aer->header_log.dw2, aer->header_log.dw3);
+                      aer->header_log.dw[0], aer->header_log.dw[1],
+                      aer->header_log.dw[2], aer->header_log.dw[3]);
        }
 }
 
 
        pci_disable_acs_redir(dev);
 }
 
+/**
+ * pcie_read_tlp_log - read TLP Header Log
+ * @dev: PCIe device
+ * @where: PCI Config offset of TLP Header Log
+ * @tlp_log: TLP Log structure to fill
+ *
+ * Fill @tlp_log from TLP Header Log registers, e.g., AER or DPC.
+ *
+ * Return: 0 on success and filled TLP Log structure, <0 on error.
+ */
+int pcie_read_tlp_log(struct pci_dev *dev, int where,
+                     struct pcie_tlp_log *tlp_log)
+{
+       int i, ret;
+
+       memset(tlp_log, 0, sizeof(*tlp_log));
+
+       for (i = 0; i < 4; i++) {
+               ret = pci_read_config_dword(dev, where + i * 4,
+                                           &tlp_log->dw[i]);
+               if (ret)
+                       return pcibios_err_to_errno(ret);
+       }
+
+       return 0;
+}
+EXPORT_SYMBOL_GPL(pcie_read_tlp_log);
+
 /**
  * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
  * @dev: PCI device to have its BARs restored
 
 
        unsigned int status;            /* COR/UNCOR Error Status */
        unsigned int mask;              /* COR/UNCOR Error Mask */
-       struct aer_header_log_regs tlp; /* TLP Header */
+       struct pcie_tlp_log tlp;        /* TLP Header */
 };
 
 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info);
 
        }
 }
 
-static void __print_tlp_header(struct pci_dev *dev,
-                              struct aer_header_log_regs *t)
+static void __print_tlp_header(struct pci_dev *dev, struct pcie_tlp_log *t)
 {
        pci_err(dev, "  TLP Header: %08x %08x %08x %08x\n",
-               t->dw0, t->dw1, t->dw2, t->dw3);
+               t->dw[0], t->dw[1], t->dw[2], t->dw[3]);
 }
 
 static void __aer_print_error(struct pci_dev *dev,
 
                if (info->status & AER_LOG_TLP_MASKS) {
                        info->tlp_header_valid = 1;
-                       pci_read_config_dword(dev,
-                               aer + PCI_ERR_HEADER_LOG, &info->tlp.dw0);
-                       pci_read_config_dword(dev,
-                               aer + PCI_ERR_HEADER_LOG + 4, &info->tlp.dw1);
-                       pci_read_config_dword(dev,
-                               aer + PCI_ERR_HEADER_LOG + 8, &info->tlp.dw2);
-                       pci_read_config_dword(dev,
-                               aer + PCI_ERR_HEADER_LOG + 12, &info->tlp.dw3);
+                       pcie_read_tlp_log(dev, aer + PCI_ERR_HEADER_LOG, &info->tlp);
                }
        }
 
 
 static void dpc_process_rp_pio_error(struct pci_dev *pdev)
 {
        u16 cap = pdev->dpc_cap, dpc_status, first_error;
-       u32 status, mask, sev, syserr, exc, dw0, dw1, dw2, dw3, log, prefix;
+       u32 status, mask, sev, syserr, exc, log, prefix;
+       struct pcie_tlp_log tlp_log;
        int i;
 
        pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, &status);
 
        if (pdev->dpc_rp_log_size < 4)
                goto clear_status;
-       pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG,
-                             &dw0);
-       pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 4,
-                             &dw1);
-       pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 8,
-                             &dw2);
-       pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 12,
-                             &dw3);
+       pcie_read_tlp_log(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG, &tlp_log);
        pci_err(pdev, "TLP Header: %#010x %#010x %#010x %#010x\n",
-               dw0, dw1, dw2, dw3);
+               tlp_log.dw[0], tlp_log.dw[1], tlp_log.dw[2], tlp_log.dw[3]);
 
        if (pdev->dpc_rp_log_size < 5)
                goto clear_status;
 
 
 struct pci_dev;
 
-struct aer_header_log_regs {
-       u32 dw0;
-       u32 dw1;
-       u32 dw2;
-       u32 dw3;
+struct pcie_tlp_log {
+       u32 dw[4];
 };
 
 struct aer_capability_regs {
        u32 cor_status;
        u32 cor_mask;
        u32 cap_control;
-       struct aer_header_log_regs header_log;
+       struct pcie_tlp_log header_log;
        u32 root_command;
        u32 root_status;
        u16 cor_err_source;
        u16 uncor_err_source;
 };
 
+int pcie_read_tlp_log(struct pci_dev *dev, int where, struct pcie_tlp_log *log);
+
 #if defined(CONFIG_PCIEAER)
 int pci_aer_clear_nonfatal_status(struct pci_dev *dev);
 int pcie_aer_is_native(struct pci_dev *dev);
 
                 const u32 status,
                 const u8 severity,
                 const u8 tlp_header_valid,
-                struct aer_header_log_regs *tlp),
+                struct pcie_tlp_log *tlp),
 
        TP_ARGS(dev_name, status, severity, tlp_header_valid, tlp),
 
                __entry->severity       = severity;
                __entry->tlp_header_valid = tlp_header_valid;
                if (tlp_header_valid) {
-                       __entry->tlp_header[0] = tlp->dw0;
-                       __entry->tlp_header[1] = tlp->dw1;
-                       __entry->tlp_header[2] = tlp->dw2;
-                       __entry->tlp_header[3] = tlp->dw3;
+                       __entry->tlp_header[0] = tlp->dw[0];
+                       __entry->tlp_header[1] = tlp->dw[1];
+                       __entry->tlp_header[2] = tlp->dw[2];
+                       __entry->tlp_header[3] = tlp->dw[3];
                }
        ),