arm64: dts: apple: s5l8960x: Add CPU caches

Add information about CPU caches in Apple A7 SoC.

Signed-off-by: Nick Chan <towinchenmi@gmail.com>
Link: https://lore.kernel.org/r/20250220-caches-v1-1-2c7011097768@gmail.com
Signed-off-by: Sven Peter <sven@svenpeter.dev>

diff --git a/arch/arm64/boot/dts/apple/s5l8960x.dtsi b/arch/arm64/boot/dts/apple/s5l8960x.dtsi
index d820b0e430507f681a5f2aa13a498be98080e1db..5b5175d6978c45052ded495fc0d18ee3a8fbfdcb 100644 (file)
--- a/arch/arm64/boot/dts/apple/s5l8960x.dtsi
+++ b/arch/arm64/boot/dts/apple/s5l8960x.dtsi
@@ -37,6 +37,9 @@
                        performance-domains = <&cpufreq>;
                        enable-method = "spin-table";
                        device_type = "cpu";
+                       next-level-cache = <&l2_cache>;
+                       i-cache-size = <0x10000>;
+                       d-cache-size = <0x10000>;
                };
 
                cpu1: cpu@1 {
@@ -47,6 +50,16 @@
                        performance-domains = <&cpufreq>;
                        enable-method = "spin-table";
                        device_type = "cpu";
+                       next-level-cache = <&l2_cache>;
+                       i-cache-size = <0x10000>;
+                       d-cache-size = <0x10000>;
+               };
+
+               l2_cache: l2-cache {
+                       compatible = "cache";
+                       cache-level = <2>;
+                       cache-unified;
+                       cache-size = <0x100000>;
                };
        };