#include <linux/mmc/sdhci-pci-data.h>
 #include <linux/acpi.h>
 
+#ifdef CONFIG_X86
+#include <asm/iosf_mbi.h>
+#endif
+
 #include "cqhci.h"
 
 #include "sdhci.h"
        .probe_slot     = pch_hc_probe_slot,
 };
 
+#ifdef CONFIG_X86
+
+#define BYT_IOSF_SCCEP                 0x63
+#define BYT_IOSF_OCP_NETCTRL0          0x1078
+#define BYT_IOSF_OCP_TIMEOUT_BASE      GENMASK(10, 8)
+
+static void byt_ocp_setting(struct pci_dev *pdev)
+{
+       u32 val = 0;
+
+       if (pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC &&
+           pdev->device != PCI_DEVICE_ID_INTEL_BYT_SDIO &&
+           pdev->device != PCI_DEVICE_ID_INTEL_BYT_SD &&
+           pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC2)
+               return;
+
+       if (iosf_mbi_read(BYT_IOSF_SCCEP, MBI_CR_READ, BYT_IOSF_OCP_NETCTRL0,
+                         &val)) {
+               dev_err(&pdev->dev, "%s read error\n", __func__);
+               return;
+       }
+
+       if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE))
+               return;
+
+       val &= ~BYT_IOSF_OCP_TIMEOUT_BASE;
+
+       if (iosf_mbi_write(BYT_IOSF_SCCEP, MBI_CR_WRITE, BYT_IOSF_OCP_NETCTRL0,
+                          val)) {
+               dev_err(&pdev->dev, "%s write error\n", __func__);
+               return;
+       }
+
+       dev_dbg(&pdev->dev, "%s completed\n", __func__);
+}
+
+#else
+
+static inline void byt_ocp_setting(struct pci_dev *pdev)
+{
+}
+
+#endif
+
 enum {
        INTEL_DSM_FNS           =  0,
        INTEL_DSM_V18_SWITCH    =  3,
 
        byt_read_dsm(slot);
 
+       byt_ocp_setting(slot->chip->pdev);
+
        ops->execute_tuning = intel_execute_tuning;
        ops->start_signal_voltage_switch = intel_start_signal_voltage_switch;
 
        return 0;
 }
 
+#ifdef CONFIG_PM_SLEEP
+
+static int byt_resume(struct sdhci_pci_chip *chip)
+{
+       byt_ocp_setting(chip->pdev);
+
+       return sdhci_pci_resume_host(chip);
+}
+
+#endif
+
+#ifdef CONFIG_PM
+
+static int byt_runtime_resume(struct sdhci_pci_chip *chip)
+{
+       byt_ocp_setting(chip->pdev);
+
+       return sdhci_pci_runtime_resume_host(chip);
+}
+
+#endif
+
 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
+#ifdef CONFIG_PM_SLEEP
+       .resume         = byt_resume,
+#endif
+#ifdef CONFIG_PM
+       .runtime_resume = byt_runtime_resume,
+#endif
        .allow_runtime_pm = true,
        .probe_slot     = byt_emmc_probe_slot,
        .quirks         = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
 };
 
 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = {
+#ifdef CONFIG_PM_SLEEP
+       .resume         = byt_resume,
+#endif
+#ifdef CONFIG_PM
+       .runtime_resume = byt_runtime_resume,
+#endif
        .quirks         = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
                          SDHCI_QUIRK_NO_LED,
        .quirks2        = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
 };
 
 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
+#ifdef CONFIG_PM_SLEEP
+       .resume         = byt_resume,
+#endif
+#ifdef CONFIG_PM
+       .runtime_resume = byt_runtime_resume,
+#endif
        .quirks         = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
                          SDHCI_QUIRK_NO_LED,
        .quirks2        = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
 };
 
 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
+#ifdef CONFIG_PM_SLEEP
+       .resume         = byt_resume,
+#endif
+#ifdef CONFIG_PM
+       .runtime_resume = byt_runtime_resume,
+#endif
        .quirks         = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
                          SDHCI_QUIRK_NO_LED,
        .quirks2        = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |