drm/amd/display: Added HPO HW control shutdown support

[Why]
HPO is only used for DP2.0. HPO HW control should be
disable when not being used to save power.

[How]
Shutdown HPO HW control during init hw.
Shutdown HPO HW control during stream disable.
Enable HPO HW control during stream enable if DP2.0.

Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Jake Wang <haonan.wang2@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index a5339796902ae844533e117f777c34f48587588c..e9bac161fd2541470a1bdad925e0e7e82e7d8744 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -675,6 +675,7 @@ struct dc_debug_options {
 #endif
        union mem_low_power_enable_options enable_mem_low_power;
        union root_clock_optimization_options root_clock_optimization;
+       bool hpo_optimization;
        bool force_vblank_alignment;
 
        /* Enable dmub aux for legacy ddc */

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index 989f5b6907e21fa9333cf944d0ff9b4b523fac20..a3fee929cd120f5e414e3f158ea74ad853df35e5 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -671,6 +671,7 @@ struct dce_hwseq_registers {
        uint32_t MC_VM_FB_LOCATION_BASE;
        uint32_t MC_VM_FB_LOCATION_TOP;
        uint32_t MC_VM_FB_OFFSET;
+       uint32_t HPO_TOP_HW_CONTROL;
 };
  /* set field name */
 #define HWS_SF(blk_name, reg_name, field_name, post_fix)\
@@ -1152,7 +1153,8 @@ struct dce_hwseq_registers {
        type DOMAIN_PGFSM_PWR_STATUS;\
        type HPO_HDMISTREAMCLK_G_GATE_DIS;\
        type DISABLE_HOSTVM_FORCE_ALLOW_PSTATE;\
-       type I2C_LIGHT_SLEEP_FORCE;
+       type I2C_LIGHT_SLEEP_FORCE;\
+       type HPO_IO_EN;
 
 struct dce_hwseq_shift {
        HWSEQ_REG_FIELD_LIST(uint8_t)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index af3e68d3e74760b890b4e1b38fd86428272ece4b..24e47df526f6a08c3a56556d1d030c2834f00a71 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1244,6 +1244,12 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx)
 #endif
        if (dc_is_dp_signal(pipe_ctx->stream->signal))
                dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_DISCONNECT_DIG_FE_BE);
+
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+       if (dc->hwseq->funcs.setup_hpo_hw_control && is_dp_128b_132b_signal(pipe_ctx))
+               dc->hwseq->funcs.setup_hpo_hw_control(dc->hwseq, false);
+#endif
+
 }
 
 void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index cfee456c6c9ab7b136dd9e4cf0d83dcb9f2f0da1..4f88376a118f8169093f1032007a9c12e7fb8c71 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -2397,6 +2397,9 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
         * BY this, it is logic clean to separate stream and link
         */
        if (is_dp_128b_132b_signal(pipe_ctx)) {
+               if (pipe_ctx->stream->ctx->dc->hwseq->funcs.setup_hpo_hw_control)
+                       pipe_ctx->stream->ctx->dc->hwseq->funcs.setup_hpo_hw_control(
+                               pipe_ctx->stream->ctx->dc->hwseq, true);
                setup_dp_hpo_stream(pipe_ctx, true);
                pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->enable_stream(
                                pipe_ctx->stream_res.hpo_dp_stream_enc);

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
index d24ad7754d710a72d6cb602c6ff54c7e7992ca6a..1b089893460a5408a43e6ef1e1d4f4481b905782 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
@@ -264,6 +264,9 @@ void dcn31_init_hw(struct dc *dc)
        if (dc->debug.enable_mem_low_power.bits.i2c)
                REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 1);
 
+       if (hws->funcs.setup_hpo_hw_control)
+               hws->funcs.setup_hpo_hw_control(hws, false);
+
        if (!dc->debug.disable_clock_gate) {
                /* enable all DCN clock gating */
                REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
@@ -597,3 +600,9 @@ void dcn31_reset_hw_ctx_wrap(
        /* New dc_state in the process of being applied to hardware. */
        dc->current_state->res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_TRANSIENT;
 }
+
+void dcn31_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable)
+{
+       if (hws->ctx->dc->debug.hpo_optimization)
+               REG_UPDATE(HPO_TOP_HW_CONTROL, HPO_IO_EN, !!enable);
+}

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.h
index 7ae45dd202d9bb5abef6d8f47530da03dbd12bf0..edfc01d6ad7378be5873ec2f6b72a63c2991320f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.h
@@ -54,5 +54,6 @@ void dcn31_reset_hw_ctx_wrap(
 bool dcn31_is_abm_supported(struct dc *dc,
                struct dc_state *context, struct dc_stream_state *stream);
 void dcn31_init_pipes(struct dc *dc, struct dc_state *context);
+void dcn31_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable);
 
 #endif /* __DC_HWSS_DCN31_H__ */

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c
index c6a737781ad18ced419498d98fb8870c4f82630d..05335a8c3c2dcffe54bb55bfebd9ba2a126e01a9 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c
@@ -137,6 +137,7 @@ static const struct hwseq_private_funcs dcn31_private_funcs = {
        .dccg_init = dcn20_dccg_init,
        .set_blend_lut = dcn30_set_blend_lut,
        .set_shaper_3dlut = dcn20_set_shaper_3dlut,
+       .setup_hpo_hw_control = dcn31_setup_hpo_hw_control,
 };
 
 void dcn31_hw_sequencer_construct(struct dc *dc)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
index 87b2c2428842901e614da779159553c3599fb0b4..18896294ae12e7e2562ca89de9edc7edd151f63e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -860,7 +860,8 @@ static const struct dccg_mask dccg_mask = {
        SR(D6VGA_CONTROL), \
        SR(DC_IP_REQUEST_CNTL), \
        SR(AZALIA_AUDIO_DTO), \
-       SR(AZALIA_CONTROLLER_CLOCK_GATING)
+       SR(AZALIA_CONTROLLER_CLOCK_GATING), \
+       SR(HPO_TOP_HW_CONTROL)
 
 static const struct dce_hwseq_registers hwseq_reg = {
                HWSEQ_DCN31_REG_LIST()
@@ -898,7 +899,8 @@ static const struct dce_hwseq_registers hwseq_reg = {
        HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
        HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
        HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \
-       HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh)
+       HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
+       HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh)
 
 static const struct dce_hwseq_shift hwseq_shift = {
                HWSEQ_DCN31_MASK_SH_LIST(__SHIFT)

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h
index f324285394be9cace132cc69cb8679de8acd4e7a..c2008258c50a5501b7bb98d5e5abdb58056ba008 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h
@@ -143,6 +143,7 @@ struct hwseq_private_funcs {
                        const struct dc_plane_state *plane_state);
        void (*PLAT_58856_wa)(struct dc_state *context,
                        struct pipe_ctx *pipe_ctx);
+       void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable);
 };
 
 struct dce_hwseq {