}
EXPORT_SYMBOL(clkdev_add);
+void __init clkdev_add_table(struct clk_lookup *cl, size_t num)
+{
+ mutex_lock(&clocks_mutex);
+ while (num--) {
+ list_add_tail(&cl->node, &clocks);
+ cl++;
+ }
+ mutex_unlock(&clocks_mutex);
+}
+
#define MAX_DEV_ID 20
#define MAX_CON_ID 16
void clkdev_add(struct clk_lookup *cl);
void clkdev_drop(struct clk_lookup *cl);
+void clkdev_add_table(struct clk_lookup *, size_t);
+int clk_add_alias(const char *, const char *, char *, struct device *);
+
#endif
chipcHw_busInterfaceClockEnable(bus_clock);
- for (i = 0; i < ARRAY_SIZE(lookups); i++)
- clkdev_add(&lookups[i]);
+ clkdev_add_table(lookups, ARRAY_SIZE(lookups));
for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
struct amba_device *d = amba_devs[i];
static int __init ep93xx_clock_init(void)
{
u32 value;
- int i;
value = __raw_readl(EP93XX_SYSCON_CLOCK_SET1);
if (!(value & 0x00800000)) { /* PLL1 bypassed? */
clk_f.rate / 1000000, clk_h.rate / 1000000,
clk_p.rate / 1000000);
- for (i = 0; i < ARRAY_SIZE(clocks); i++)
- clkdev_add(&clocks[i]);
+ clkdev_add_table(clocks, ARRAY_SIZE(clocks));
return 0;
}
arch_initcall(ep93xx_clock_init);
{
int i;
- for (i = 0; i < ARRAY_SIZE(lookups); i++)
- clkdev_add(&lookups[i]);
+ clkdev_add_table(lookups, ARRAY_SIZE(lookups));
for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
struct amba_device *d = amba_devs[i];
{
int i;
- for (i = 0; i < ARRAY_SIZE(cp_lookups); i++)
- clkdev_add(&cp_lookups[i]);
-
+ clkdev_add_table(cp_lookups, ARRAY_SIZE(cp_lookups));
platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
return rate;
}
EXPORT_SYMBOL(clk_get_rate);
-
-void clks_register(struct clk_lookup *clks, size_t num)
-{
- int i;
-
- for (i = 0; i < num; i++)
- clkdev_add(&clks[i]);
-}
extern struct clk clk_pxa168_gpio;
extern struct clk clk_pxa168_timers;
-
-extern void clks_register(struct clk_lookup *, size_t);
mfp_init_base(MFPR_VIRT_BASE);
mfp_init_addr(pxa168_mfp_addr_map);
pxa_init_dma(IRQ_PXA168_DMA_INT0, 32);
- clks_register(ARRAY_AND_SIZE(pxa168_clkregs));
+ clkdev_add_table(ARRAY_AND_SIZE(pxa168_clkregs));
}
return 0;
mfp_init_base(MFPR_VIRT_BASE);
mfp_init_addr(pxa910_mfp_addr_map);
pxa_init_dma(IRQ_PXA910_DMA_INT0, 32);
- clks_register(ARRAY_AND_SIZE(pxa910_clkregs));
+ clkdev_add_table(ARRAY_AND_SIZE(pxa910_clkregs));
}
return 0;
int __init mx1_clocks_init(unsigned long fref)
{
unsigned int reg;
- int i;
/* disable clocks we are able to */
__raw_writel(0, SCM_GCCR);
reg = (reg & CCM_CSCR_CLKO_MASK) >> CCM_CSCR_CLKO_OFFSET;
clko_clk.parent = (struct clk *)clko_clocks[reg];
- for (i = 0; i < ARRAY_SIZE(lookups); i++)
- clkdev_add(&lookups[i]);
+ clkdev_add_table(lookups, ARRAY_SIZE(lookups));
clk_enable(&hclk);
clk_enable(&fclk);
*/
int __init mx21_clocks_init(unsigned long lref, unsigned long href)
{
- int i;
u32 cscr;
external_low_reference = lref;
else
spll_clk.parent = &fpm_clk;
- for (i = 0; i < ARRAY_SIZE(lookups); i++)
- clkdev_add(&lookups[i]);
+ clkdev_add_table(lookups, ARRAY_SIZE(lookups));
/* Turn off all clock gates */
__raw_writel(0, CCM_PCCR0);
int __init mx27_clocks_init(unsigned long fref)
{
u32 cscr = __raw_readl(CCM_CSCR);
- int i;
external_high_reference = fref;
to2_adjust_clocks();
- for (i = 0; i < ARRAY_SIZE(lookups); i++)
- clkdev_add(&lookups[i]);
+ clkdev_add_table(lookups, ARRAY_SIZE(lookups));
/* Turn off all clocks we do not need */
__raw_writel(0, CCM_PCCR0);
int __init mx25_clocks_init(unsigned long fref)
{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(lookups); i++)
- clkdev_add(&lookups[i]);
-
+ clkdev_add_table(lookups, ARRAY_SIZE(lookups));
mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
return 0;
int __init mx35_clocks_init()
{
- int i;
unsigned int ll = 0;
#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
ll = (3 << 16);
#endif
- for (i = 0; i < ARRAY_SIZE(lookups); i++)
- clkdev_add(&lookups[i]);
+ clkdev_add_table(lookups, ARRAY_SIZE(lookups));
/* Turn off all clocks except the ones we need to survive, namely:
* EMI, GPIO1/2/3, GPT, IOMUX, MAX and eventually uart
int __init mx31_clocks_init(unsigned long fref)
{
u32 reg;
- int i;
ckih_rate = fref;
- for (i = 0; i < ARRAY_SIZE(lookups); i++)
- clkdev_add(&lookups[i]);
+ clkdev_add_table(lookups, ARRAY_SIZE(lookups));
/* change the csi_clk parent if necessary */
reg = __raw_readl(MXC_CCM_CCMR);
int __init mxc91231_clocks_init(unsigned long fref)
{
void __iomem *gpt_base;
- int i;
ckih_rate = fref;
sdhc_clk[0].parent = clk_sdhc_parent(&sdhc_clk[0]);
sdhc_clk[1].parent = clk_sdhc_parent(&sdhc_clk[1]);
- for (i = 0; i < ARRAY_SIZE(lookups); i++)
- clkdev_add(&lookups[i]);
+ clkdev_add_table(lookups, ARRAY_SIZE(lookups));
gpt_base = MXC91231_IO_ADDRESS(MXC91231_GPT1_BASE_ADDR);
mxc_timer_init(&gpt_clk, gpt_base, MXC91231_INT_GPT);
.enable = clk_cken_enable,
.disable = clk_cken_disable,
};
-
-void clks_register(struct clk_lookup *clks, size_t num)
-{
- int i;
-
- for (i = 0; i < num; i++)
- clkdev_add(&clks[i]);
-}
extern void clk_pxa3xx_cken_disable(struct clk *);
#endif
-void clks_register(struct clk_lookup *clks, size_t num);
-int clk_add_alias(const char *alias, const char *alias_name, char *id,
- struct device *dev);
-
void eseries_register_clks(void)
{
- clks_register(eseries_clkregs, ARRAY_SIZE(eseries_clkregs));
+ clkdev_add_table(eseries_clkregs, ARRAY_SIZE(eseries_clkregs));
}
reset_status = RCSR;
- clks_register(pxa25x_clkregs, ARRAY_SIZE(pxa25x_clkregs));
+ clkdev_add_table(pxa25x_clkregs, ARRAY_SIZE(pxa25x_clkregs));
if ((ret = pxa_init_dma(IRQ_DMA, 16)))
return ret;
/* Only add HWUART for PXA255/26x; PXA210/250 do not have it. */
if (cpu_is_pxa255())
- clks_register(&pxa25x_hwuart_clkreg, 1);
+ clkdev_add(&pxa25x_hwuart_clkreg);
return ret;
}
reset_status = RCSR;
- clks_register(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs));
+ clkdev_add_table(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs));
if ((ret = pxa_init_dma(IRQ_DMA, 32)))
return ret;
if (cpu_is_pxa300() || cpu_is_pxa310()) {
mfp_init_base(io_p2v(MFPR_BASE));
mfp_init_addr(pxa300_mfp_addr_map);
- clks_register(ARRAY_AND_SIZE(common_clkregs));
+ clkdev_add_table(ARRAY_AND_SIZE(common_clkregs));
}
if (cpu_is_pxa310()) {
mfp_init_addr(pxa310_mfp_addr_map);
- clks_register(ARRAY_AND_SIZE(pxa310_clkregs));
+ clkdev_add_table(ARRAY_AND_SIZE(pxa310_clkregs));
}
return 0;
if (cpu_is_pxa320()) {
mfp_init_base(io_p2v(MFPR_BASE));
mfp_init_addr(pxa320_mfp_addr_map);
- clks_register(ARRAY_AND_SIZE(pxa320_clkregs));
+ clkdev_add_table(ARRAY_AND_SIZE(pxa320_clkregs));
}
return 0;
*/
ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
- clks_register(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs));
+ clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs));
if ((ret = pxa_init_dma(IRQ_DMA, 32)))
return ret;
static int __init clk_init(void)
{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(lookups); i++)
- clkdev_add(&lookups[i]);
+ clkdev_add_table(lookups, ARRAY_SIZE(lookups));
return 0;
}
arch_initcall(clk_init);
static void __init clk_register(void)
{
- int i;
-
/* Register the lookups */
- for (i = 0; i < ARRAY_SIZE(lookups); i++)
- clkdev_add(&lookups[i]);
+ clkdev_add_table(lookups, ARRAY_SIZE(lookups));
}
/*
static int __init clk_init(void)
{
- int i;
-
/* register the clock lookups */
- for (i = 0; i < ARRAY_SIZE(lookups); i++)
- clkdev_add(&lookups[i]);
+ clkdev_add_table(lookups, ARRAY_SIZE(lookups));
return 0;
}
arch_initcall(clk_init);
{
int i;
- for (i = 0; i < ARRAY_SIZE(lookups); i++)
- clkdev_add(&lookups[i]);
+ clkdev_add_table(lookups, ARRAY_SIZE(lookups));
platform_device_register(&versatile_flash_device);
platform_device_register(&versatile_i2c_device);
__raw_writel(clken, W90X900_VA_CLKPWR + SUBCLK);
}
-
-
-void clks_register(struct clk_lookup *clks, size_t num)
-{
- int i;
-
- for (i = 0; i < num; i++)
- clkdev_add(&clks[i]);
-}
void nuc900_clk_enable(struct clk *clk, int enable);
void nuc900_subclk_enable(struct clk *clk, int enable);
-void clks_register(struct clk_lookup *clks, size_t num);
struct clk {
unsigned long cken;
void __init nuc900_init_clocks(void)
{
- clks_register(nuc900_clkregs, ARRAY_SIZE(nuc900_clkregs));
+ clkdev_add_table(nuc900_clkregs, ARRAY_SIZE(nuc900_clkregs));
}
if (ops && ops->set_parent)
ops->set_parent(cl->clk, cl->clk->parent);
}
-
- clkdev_add(cl);
}
+ clkdev_add_table(onchip_clks, ARRAY_SIZE(onchip_clks));
return 0;
}
projects / users / jedix / linux-maple.git / commitdiff