clocksource/drivers/tegra: Set and use timer's period

The of_clk structure has a period field that is set up initially by
timer_of_clk_init(), that period value need to be adjusted for a case of
TIMER1-9 that are running at a fixed rate that doesn't match the clock's
rate. Note that the period value is currently used only by some of the
clocksource drivers internally and hence this is just a minor cleanup
change that doesn't fix anything.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>

diff --git a/drivers/clocksource/timer-tegra.c b/drivers/clocksource/timer-tegra.c
index f172a57cc5fe7b7b14c773165a4f2b49892640b2..41257f89a216bd831080366946dba56e0cceeed6 100644 (file)
--- a/drivers/clocksource/timer-tegra.c
+++ b/drivers/clocksource/timer-tegra.c
@@ -73,9 +73,9 @@ static int tegra_timer_shutdown(struct clock_event_device *evt)
 static int tegra_timer_set_periodic(struct clock_event_device *evt)
 {
        void __iomem *reg_base = timer_of_base(to_timer_of(evt));
+       unsigned long period = timer_of_period(to_timer_of(evt));
 
-       writel_relaxed(TIMER_PTV_EN | TIMER_PTV_PER |
-                      ((timer_of_rate(to_timer_of(evt)) / HZ) - 1),
+       writel_relaxed(TIMER_PTV_EN | TIMER_PTV_PER | (period - 1),
                       reg_base + TIMER_PTV);
 
        return 0;
@@ -299,6 +299,7 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20,
                cpu_to->clkevt.rating = rating;
                cpu_to->clkevt.cpumask = cpumask_of(cpu);
                cpu_to->of_base.base = timer_reg_base + base;
+               cpu_to->of_clk.period = rate / HZ;
                cpu_to->of_clk.rate = rate;
 
                irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN);