static void l2x0_resume(void)
 {
-       if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
-               /* restore aux ctrl and enable l2 */
-               l2x0_unlock(readl_relaxed(l2x0_base + L2X0_CACHE_ID));
-
-               writel_relaxed(l2x0_saved_regs.aux_ctrl, l2x0_base +
-                       L2X0_AUX_CTRL);
-
-               l2x0_inv_all();
+       void __iomem *base = l2x0_base;
 
-               writel_relaxed(L2X0_CTRL_EN, l2x0_base + L2X0_CTRL);
-       }
+       if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN))
+               l2x0_enable(base, l2x0_saved_regs.aux_ctrl, 0);
 }
 
 static const struct l2c_init_data l2x0_init_fns __initconst = {
  *     Affects: store buffer
  *     store buffer is not automatically drained.
  */
-static void __init pl310_save(void __iomem *base)
+static void __init l2c310_save(void __iomem *base)
 {
-       u32 l2x0_revision = readl_relaxed(base + L2X0_CACHE_ID) &
-               L2X0_CACHE_ID_RTL_MASK;
+       unsigned revision;
 
        l2x0_saved_regs.tag_latency = readl_relaxed(base +
                L2X0_TAG_LATENCY_CTRL);
        l2x0_saved_regs.filter_start = readl_relaxed(base +
                L2X0_ADDR_FILTER_START);
 
-       if (l2x0_revision >= L310_CACHE_ID_RTL_R2P0) {
-               /*
-                * From r2p0, there is Prefetch offset/control register
-                */
+       revision = readl_relaxed(base + L2X0_CACHE_ID) &
+                       L2X0_CACHE_ID_RTL_MASK;
+
+       /* From r2p0, there is Prefetch offset/control register */
+       if (revision >= L310_CACHE_ID_RTL_R2P0)
                l2x0_saved_regs.prefetch_ctrl = readl_relaxed(base +
-                       L2X0_PREFETCH_CTRL);
-               /*
-                * From r3p0, there is Power control register
-                */
-               if (l2x0_revision >= L310_CACHE_ID_RTL_R3P0)
-                       l2x0_saved_regs.pwr_ctrl = readl_relaxed(base +
-                               L2X0_POWER_CTRL);
-       }
+                                                       L2X0_PREFETCH_CTRL);
+
+       /* From r3p0, there is Power control register */
+       if (revision >= L310_CACHE_ID_RTL_R3P0)
+               l2x0_saved_regs.pwr_ctrl = readl_relaxed(base +
+                                                       L2X0_POWER_CTRL);
 }
 
-static void pl310_resume(void)
+static void l2c310_resume(void)
 {
-       u32 l2x0_revision;
+       void __iomem *base = l2x0_base;
+
+       if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN)) {
+               unsigned revision;
 
-       if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
                /* restore pl310 setup */
                writel_relaxed(l2x0_saved_regs.tag_latency,
-                       l2x0_base + L2X0_TAG_LATENCY_CTRL);
+                              base + L2X0_TAG_LATENCY_CTRL);
                writel_relaxed(l2x0_saved_regs.data_latency,
-                       l2x0_base + L2X0_DATA_LATENCY_CTRL);
+                              base + L2X0_DATA_LATENCY_CTRL);
                writel_relaxed(l2x0_saved_regs.filter_end,
-                       l2x0_base + L2X0_ADDR_FILTER_END);
+                              base + L2X0_ADDR_FILTER_END);
                writel_relaxed(l2x0_saved_regs.filter_start,
-                       l2x0_base + L2X0_ADDR_FILTER_START);
+                              base + L2X0_ADDR_FILTER_START);
 
-               l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) &
-                       L2X0_CACHE_ID_RTL_MASK;
+               revision = readl_relaxed(base + L2X0_CACHE_ID) &
+                               L2X0_CACHE_ID_RTL_MASK;
 
-               if (l2x0_revision >= L310_CACHE_ID_RTL_R2P0) {
+               if (revision >= L310_CACHE_ID_RTL_R2P0)
                        writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
-                               l2x0_base + L2X0_PREFETCH_CTRL);
-                       if (l2x0_revision >= L310_CACHE_ID_RTL_R3P0)
-                               writel_relaxed(l2x0_saved_regs.pwr_ctrl,
-                                       l2x0_base + L2X0_POWER_CTRL);
-               }
-       }
+                                      base + L2X0_PREFETCH_CTRL);
+               if (revision >= L310_CACHE_ID_RTL_R3P0)
+                       writel_relaxed(l2x0_saved_regs.pwr_ctrl,
+                                      base + L2X0_POWER_CTRL);
 
-       l2x0_resume();
+               l2c_enable(base, l2x0_saved_regs.aux_ctrl, 8);
+       }
 }
 
 static void __init l2c310_fixup(void __iomem *base, u32 cache_id,
        .num_lock = 8,
        .enable = l2c_enable,
        .fixup = l2c310_fixup,
-       .save = pl310_save,
+       .save = l2c310_save,
        .outer_cache = {
                .inv_range = l2x0_inv_range,
                .clean_range = l2x0_clean_range,
                .flush_all = l2x0_flush_all,
                .disable = l2x0_disable,
                .sync = l2x0_cache_sync,
-               .resume = pl310_resume,
+               .resume = l2c310_resume,
        },
 };
 
        .of_parse = pl310_of_parse,
        .enable = l2c_enable,
        .fixup = l2c310_fixup,
-       .save  = pl310_save,
+       .save  = l2c310_save,
        .outer_cache = {
                .inv_range   = l2x0_inv_range,
                .clean_range = l2x0_clean_range,
                .flush_all   = l2x0_flush_all,
                .disable     = l2x0_disable,
                .sync        = l2x0_cache_sync,
-               .resume      = pl310_resume,
+               .resume      = l2c310_resume,
        },
 };
 
 
 static void aurora_resume(void)
 {
-       if (!(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
-               writel_relaxed(l2x0_saved_regs.aux_ctrl,
-                               l2x0_base + L2X0_AUX_CTRL);
-               writel_relaxed(l2x0_saved_regs.ctrl, l2x0_base + L2X0_CTRL);
+       void __iomem *base = l2x0_base;
+
+       if (!(readl(base + L2X0_CTRL) & L2X0_CTRL_EN)) {
+               writel_relaxed(l2x0_saved_regs.aux_ctrl, base + L2X0_AUX_CTRL);
+               writel_relaxed(l2x0_saved_regs.ctrl, base + L2X0_CTRL);
        }
 }
 
        .of_parse = pl310_of_parse,
        .enable = l2c_enable,
        .fixup = l2c310_fixup,
-       .save  = pl310_save,
+       .save  = l2c310_save,
        .outer_cache = {
                .inv_range   = bcm_inv_range,
                .clean_range = bcm_clean_range,
                .flush_all   = l2x0_flush_all,
                .disable     = l2x0_disable,
                .sync        = l2x0_cache_sync,
-               .resume      = pl310_resume,
+               .resume      = l2c310_resume,
        },
 };
 
 
 static void tauros3_resume(void)
 {
-       if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
+       void __iomem *base = l2x0_base;
+
+       if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN)) {
                writel_relaxed(l2x0_saved_regs.aux2_ctrl,
-                              l2x0_base + TAUROS3_AUX2_CTRL);
+                              base + TAUROS3_AUX2_CTRL);
                writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
-                              l2x0_base + L2X0_PREFETCH_CTRL);
-       }
+                              base + L2X0_PREFETCH_CTRL);
 
-       l2x0_resume();
+               l2c_enable(base, l2x0_saved_regs.aux_ctrl, 8);
+       }
 }
 
 static const struct l2c_init_data of_tauros3_data __initconst = {