arm64: dts: qcom: sm6375: Bump CPU rail power collapse index

In preparation for supporting a less-deep sleep state, rename the
existing rail power off from _0 to _1.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230303-topic-sm6375_features0_dts-v2-12-708b8191f7eb@linaro.org

diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi
index 036e36ceebb59f4e5f3a33bbc6c2fbbdee0bb088..6b75d86110771632b46e2ac9be2b3f340f5599d9 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm6375.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi
@@ -214,7 +214,7 @@
                idle-states {
                        entry-method = "psci";
 
-                       LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
+                       LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
                                compatible = "arm,idle-state";
                                idle-state-name = "silver-rail-power-collapse";
                                arm,psci-suspend-param = <0x40000004>;
@@ -224,7 +224,7 @@
                                local-timer-stop;
                        };
 
-                       BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
+                       BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
                                compatible = "arm,idle-state";
                                idle-state-name = "gold-rail-power-collapse";
                                arm,psci-suspend-param = <0x40000004>;
@@ -275,49 +275,49 @@
                CPU_PD0: power-domain-cpu0 {
                        #power-domain-cells = <0>;
                        power-domains = <&CLUSTER_PD>;
-                       domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+                       domain-idle-states = <&LITTLE_CPU_SLEEP_1>;
                };
 
                CPU_PD1: power-domain-cpu1 {
                        #power-domain-cells = <0>;
                        power-domains = <&CLUSTER_PD>;
-                       domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+                       domain-idle-states = <&LITTLE_CPU_SLEEP_1>;
                };
 
                CPU_PD2: power-domain-cpu2 {
                        #power-domain-cells = <0>;
                        power-domains = <&CLUSTER_PD>;
-                       domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+                       domain-idle-states = <&LITTLE_CPU_SLEEP_1>;
                };
 
                CPU_PD3: power-domain-cpu3 {
                        #power-domain-cells = <0>;
                        power-domains = <&CLUSTER_PD>;
-                       domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+                       domain-idle-states = <&LITTLE_CPU_SLEEP_1>;
                };
 
                CPU_PD4: power-domain-cpu4 {
                        #power-domain-cells = <0>;
                        power-domains = <&CLUSTER_PD>;
-                       domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+                       domain-idle-states = <&LITTLE_CPU_SLEEP_1>;
                };
 
                CPU_PD5: power-domain-cpu5 {
                        #power-domain-cells = <0>;
                        power-domains = <&CLUSTER_PD>;
-                       domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+                       domain-idle-states = <&LITTLE_CPU_SLEEP_1>;
                };
 
                CPU_PD6: power-domain-cpu6 {
                        #power-domain-cells = <0>;
                        power-domains = <&CLUSTER_PD>;
-                       domain-idle-states = <&BIG_CPU_SLEEP_0>;
+                       domain-idle-states = <&BIG_CPU_SLEEP_1>;
                };
 
                CPU_PD7: power-domain-cpu7 {
                        #power-domain-cells = <0>;
                        power-domains = <&CLUSTER_PD>;
-                       domain-idle-states = <&BIG_CPU_SLEEP_0>;
+                       domain-idle-states = <&BIG_CPU_SLEEP_1>;
                };
 
                CLUSTER_PD: power-domain-cpu-cluster0 {