arm64: dts: renesas: r9a09g057: Add WDT0-WDT3 nodes

Add WDT0-WDT3 nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240828124134.188864-8-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
index 9f6939a4e40ff0b1d1a3d6d4cd7eeac9d9541831..1ad5a1b6917fee3e11203a5a62350d8c824bc73a 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -201,6 +201,46 @@
                        status = "disabled";
                };
 
+               wdt0: watchdog@11c00400 {
+                       compatible = "renesas,r9a09g057-wdt";
+                       reg = <0 0x11c00400 0 0x400>;
+                       clocks = <&cpg CPG_MOD 0x4b>, <&cpg CPG_MOD 0x4c>;
+                       clock-names = "pclk", "oscclk";
+                       resets = <&cpg 0x75>;
+                       power-domains = <&cpg>;
+                       status = "disabled";
+               };
+
+               wdt1: watchdog@14400000 {
+                       compatible = "renesas,r9a09g057-wdt";
+                       reg = <0 0x14400000 0 0x400>;
+                       clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>;
+                       clock-names = "pclk", "oscclk";
+                       resets = <&cpg 0x76>;
+                       power-domains = <&cpg>;
+                       status = "disabled";
+               };
+
+               wdt2: watchdog@13000000 {
+                       compatible = "renesas,r9a09g057-wdt";
+                       reg = <0 0x13000000 0 0x400>;
+                       clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>;
+                       clock-names = "pclk", "oscclk";
+                       resets = <&cpg 0x77>;
+                       power-domains = <&cpg>;
+                       status = "disabled";
+               };
+
+               wdt3: watchdog@13000400 {
+                       compatible = "renesas,r9a09g057-wdt";
+                       reg = <0 0x13000400 0 0x400>;
+                       clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>;
+                       clock-names = "pclk", "oscclk";
+                       resets = <&cpg 0x78>;
+                       power-domains = <&cpg>;
+                       status = "disabled";
+               };
+
                scif: serial@11c01400 {
                        compatible = "renesas,scif-r9a09g057";
                        reg = <0 0x11c01400 0 0x400>;