drm/i915: Classify the engines in class + instance

In such a way that vcs and vcs2 are just two different instances (0 and 1)
of the same engine class (VIDEO_DECODE_CLASS).

v2: Align the instance types (Tvrtko)

v3: Don't use enums for bspec-defined stuff (Michal)

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1491834873-9345-2-git-send-email-oscar.mateo@intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 11b12f4124920b07a65aaf7e02b81c8784bece46..4c72adae368ba3cdfbf2435cbc44eb95b847acd3 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -85,6 +85,14 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define VECS_HW                3
 #define VCS2_HW                4
 
+/* Engine class */
+
+#define RENDER_CLASS           0
+#define VIDEO_DECODE_CLASS     1
+#define VIDEO_ENHANCEMENT_CLASS        2
+#define COPY_ENGINE_CLASS      3
+#define OTHER_CLASS            4
+
 /* PCI config space */
 
 #define MCHBAR_I915 0x44

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 92f871cf32652e2a590d2df5537aa51ba37fbcb9..bb229274c30d91437b5eebcd8b3b41a765a5e7e8 100644 (file)
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -30,6 +30,8 @@ static const struct engine_info {
        const char *name;
        unsigned int exec_id;
        unsigned int hw_id;
+       u8 class;
+       u8 instance;
        u32 mmio_base;
        unsigned irq_shift;
        int (*init_legacy)(struct intel_engine_cs *engine);
@@ -39,6 +41,8 @@ static const struct engine_info {
                .name = "rcs",
                .hw_id = RCS_HW,
                .exec_id = I915_EXEC_RENDER,
+               .class = RENDER_CLASS,
+               .instance = 0,
                .mmio_base = RENDER_RING_BASE,
                .irq_shift = GEN8_RCS_IRQ_SHIFT,
                .init_execlists = logical_render_ring_init,
@@ -48,6 +52,8 @@ static const struct engine_info {
                .name = "bcs",
                .hw_id = BCS_HW,
                .exec_id = I915_EXEC_BLT,
+               .class = COPY_ENGINE_CLASS,
+               .instance = 0,
                .mmio_base = BLT_RING_BASE,
                .irq_shift = GEN8_BCS_IRQ_SHIFT,
                .init_execlists = logical_xcs_ring_init,
@@ -57,6 +63,8 @@ static const struct engine_info {
                .name = "vcs",
                .hw_id = VCS_HW,
                .exec_id = I915_EXEC_BSD,
+               .class = VIDEO_DECODE_CLASS,
+               .instance = 0,
                .mmio_base = GEN6_BSD_RING_BASE,
                .irq_shift = GEN8_VCS1_IRQ_SHIFT,
                .init_execlists = logical_xcs_ring_init,
@@ -66,6 +74,8 @@ static const struct engine_info {
                .name = "vcs2",
                .hw_id = VCS2_HW,
                .exec_id = I915_EXEC_BSD,
+               .class = VIDEO_DECODE_CLASS,
+               .instance = 1,
                .mmio_base = GEN8_BSD2_RING_BASE,
                .irq_shift = GEN8_VCS2_IRQ_SHIFT,
                .init_execlists = logical_xcs_ring_init,
@@ -75,6 +85,8 @@ static const struct engine_info {
                .name = "vecs",
                .hw_id = VECS_HW,
                .exec_id = I915_EXEC_VEBOX,
+               .class = VIDEO_ENHANCEMENT_CLASS,
+               .instance = 0,
                .mmio_base = VEBOX_RING_BASE,
                .irq_shift = GEN8_VECS_IRQ_SHIFT,
                .init_execlists = logical_xcs_ring_init,
@@ -101,6 +113,8 @@ intel_engine_setup(struct drm_i915_private *dev_priv,
        engine->hw_id = engine->guc_id = info->hw_id;
        engine->mmio_base = info->mmio_base;
        engine->irq_shift = info->irq_shift;
+       engine->class = info->class;
+       engine->instance = info->instance;
 
        /* Nothing to do here, execute in order of dependencies */
        engine->schedule = NULL;

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index cbe61d3f31da9cc0a5bbf10b8350df2d3b112d2e..f54fe7d063a802fb469988cb70f3ef9b83cf804f 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -193,6 +193,10 @@ struct intel_engine_cs {
        enum intel_engine_id id;
        unsigned int exec_id;
        unsigned int hw_id;
+
+       u8 class;
+       u8 instance;
+
        unsigned int guc_id;
        u32             mmio_base;
        unsigned int irq_shift;