drm/xe: Fix ring flush invalidation

Emit_flush_invalidate() is incorrectly marking the write to LRC_PPHWSP as
a GGTT write and also writing an atypical ~0 dword as the payload. Fix it.

While at it drop the unused flags argument.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250307111402.26577-3-tvrtko.ursulin@igalia.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
index d2f604aa96faeb0cfe398284e4012d1a9290fa75..3d1b4d3d788f40065906d0a8be19ada28d3363bb 100644 (file)
--- a/drivers/gpu/drm/xe/xe_ring_ops.c
+++ b/drivers/gpu/drm/xe/xe_ring_ops.c
@@ -111,16 +111,13 @@ static int emit_bb_start(u64 batch_addr, u32 ppgtt_flag, u32 *dw, int i)
        return i;
 }
 
-static int emit_flush_invalidate(u32 flag, u32 *dw, int i)
+static int emit_flush_invalidate(u32 *dw, int i)
 {
-       dw[i] = MI_FLUSH_DW;
-       dw[i] |= flag;
-       dw[i++] |= MI_INVALIDATE_TLB | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_IMM_DW |
-               MI_FLUSH_DW_STORE_INDEX;
-
-       dw[i++] = LRC_PPHWSP_FLUSH_INVAL_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
+       dw[i++] = MI_FLUSH_DW | MI_INVALIDATE_TLB | MI_FLUSH_DW_OP_STOREDW |
+                 MI_FLUSH_IMM_DW | MI_FLUSH_DW_STORE_INDEX;
+       dw[i++] = LRC_PPHWSP_FLUSH_INVAL_SCRATCH_ADDR;
+       dw[i++] = 0;
        dw[i++] = 0;
-       dw[i++] = ~0U;
 
        return i;
 }
@@ -413,7 +410,7 @@ static void emit_migration_job_gen12(struct xe_sched_job *job,
        if (!IS_SRIOV_VF(gt_to_xe(job->q->gt))) {
                /* XXX: Do we need this? Leaving for now. */
                dw[i++] = preparser_disable(true);
-               i = emit_flush_invalidate(0, dw, i);
+               i = emit_flush_invalidate(dw, i);
                dw[i++] = preparser_disable(false);
        }