#define ADV7180_REG_VPP_SLAVE_ADDR     0xFD
 #define ADV7180_REG_CSI_SLAVE_ADDR     0xFE
 
+#define ADV7180_REG_FLCONTROL 0x40e0
+#define ADV7180_FLCONTROL_FL_ENABLE 0x1
+
 #define ADV7180_CSI_REG_PWRDN  0x00
 #define ADV7180_CSI_PWRDN      0x80
 
 #define ADV7180_DEFAULT_CSI_I2C_ADDR 0x44
 #define ADV7180_DEFAULT_VPP_I2C_ADDR 0x42
 
+#define V4L2_CID_ADV_FAST_SWITCH       (V4L2_CID_USER_ADV7180_BASE + 0x00)
+
 struct adv7180_state;
 
 #define ADV7180_FLAG_RESET_POWERED     BIT(0)
                        break;
                ret = adv7180_write(state, ADV7180_REG_SD_SAT_CR, val);
                break;
+       case V4L2_CID_ADV_FAST_SWITCH:
+               if (ctrl->val) {
+                       /* ADI required write */
+                       adv7180_write(state, 0x80d9, 0x44);
+                       adv7180_write(state, ADV7180_REG_FLCONTROL,
+                               ADV7180_FLCONTROL_FL_ENABLE);
+               } else {
+                       /* ADI required write */
+                       adv7180_write(state, 0x80d9, 0xc4);
+                       adv7180_write(state, ADV7180_REG_FLCONTROL, 0x00);
+               }
+               break;
        default:
                ret = -EINVAL;
        }
        .s_ctrl = adv7180_s_ctrl,
 };
 
+static const struct v4l2_ctrl_config adv7180_ctrl_fast_switch = {
+       .ops = &adv7180_ctrl_ops,
+       .id = V4L2_CID_ADV_FAST_SWITCH,
+       .name = "Fast Switching",
+       .type = V4L2_CTRL_TYPE_BOOLEAN,
+       .min = 0,
+       .max = 1,
+       .step = 1,
+};
+
 static int adv7180_init_controls(struct adv7180_state *state)
 {
        v4l2_ctrl_handler_init(&state->ctrl_hdl, 4);
        v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
                          V4L2_CID_HUE, ADV7180_HUE_MIN,
                          ADV7180_HUE_MAX, 1, ADV7180_HUE_DEF);
+       v4l2_ctrl_new_custom(&state->ctrl_hdl, &adv7180_ctrl_fast_switch, NULL);
+
        state->sd.ctrl_handler = &state->ctrl_hdl;
        if (state->ctrl_hdl.error) {
                int err = state->ctrl_hdl.error;
 
  * We reserve 16 controls for this driver. */
 #define V4L2_CID_USER_SAA7134_BASE             (V4L2_CID_USER_BASE + 0x1060)
 
+/* The base for the adv7180 driver controls.
+ * We reserve 16 controls for this driver. */
+#define V4L2_CID_USER_ADV7180_BASE             (V4L2_CID_USER_BASE + 0x1070)
+
 /* MPEG-class control IDs */
 /* The MPEG controls are applicable to all codec controls
  * and the 'MPEG' part of the define is historical */