ARM: dts: imx6dl-eckelmann-ci4x10: configure ethernet reference clock parent

On this board the PHY is the ref clock provider. So, configure ethernet
reference clock as input.

Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts b/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts
index 864dc5018451f353287ff0b799f1527f14bdf44d..33825b5a8f26c8af3b24a42a1531d4c8f8acb773 100644 (file)
--- a/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts
+++ b/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts
@@ -28,6 +28,7 @@
                compatible = "fixed-clock";
                #clock-cells = <0>;
                clock-frequency = <50000000>;
+               clock-output-names = "enet_ref_pad";
        };
 
        reg_usb_h1_vbus: regulator-usb-h1-vbus {
@@ -64,6 +65,13 @@
        status = "okay";
 };
 
+&clks {
+       clocks = <&rmii_clk>;
+       clock-names = "enet_ref_pad";
+       assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
+       assigned-clock-parents = <&rmii_clk>;
+};
+
 &ecspi2 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_ecspi2>;
@@ -297,11 +305,6 @@
        phy-mode = "rmii";
        phy-reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
        phy-handle = <&phy>;
-       clocks = <&clks IMX6QDL_CLK_ENET>,
-                <&clks IMX6QDL_CLK_ENET>,
-                <&rmii_clk>,
-                <&clks IMX6QDL_CLK_ENET_REF>;
-       clock-names = "ipg", "ahb", "ptp", "enet_out";
        status = "okay";
 
        mdio {