drm/amdgpu/vce4: Remove vce interrupt enable related code for sriov

Interrupt enable is contained in vce init table and this register could
not be accessed in secure ASICs, so just remove it.

Signed-off-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Xiangliang.Yu <Xiangliang.Yu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index 28532e39d0b531efb5b2e1de1fd398035819963a..9e0050d8b85294c5f363410bc16926fcb3075e75 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -992,11 +992,13 @@ static int vce_v4_0_set_interrupt_state(struct amdgpu_device *adev,
 {
        uint32_t val = 0;
 
-       if (state == AMDGPU_IRQ_STATE_ENABLE)
-               val |= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK;
+       if (!amdgpu_sriov_vf(adev)) {
+               if (state == AMDGPU_IRQ_STATE_ENABLE)
+                       val |= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK;
 
-       WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN), val,
-                       ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
+               WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN), val,
+                               ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
+       }
        return 0;
 }