]> www.infradead.org Git - users/dwmw2/linux.git/commitdiff
Merge branch 'x86/urgent' into x86/fpu, to resolve a conflict
authorIngo Molnar <mingo@kernel.org>
Sat, 16 Oct 2021 13:17:46 +0000 (15:17 +0200)
committerIngo Molnar <mingo@kernel.org>
Sat, 16 Oct 2021 13:17:46 +0000 (15:17 +0200)
Resolve the conflict between these commits:

   x86/fpu:      1193f408cd51 ("x86/fpu/signal: Change return type of __fpu_restore_sig() to boolean")

   x86/urgent:   d298b03506d3 ("x86/fpu: Restore the masking out of reserved MXCSR bits")
                 b2381acd3fd9 ("x86/fpu: Mask out the invalid MXCSR bits properly")

 Conflicts:
        arch/x86/kernel/fpu/signal.c

Signed-off-by: Ingo Molnar <mingo@kernel.org>
1  2 
arch/x86/kernel/cpu/mce/core.c
arch/x86/kernel/fpu/signal.c
arch/x86/net/bpf_jit_comp.c
scripts/sorttable.c

Simple merge
index 39c7bae97daf1157f7436b55c9b43ed89e3555b3,831b25c5e70581aeb490e951a7bb8842a5dbc0be..51c4915a35f0aabad1efc4522e12e8f78e9a4b24
@@@ -382,11 -377,16 +382,16 @@@ static bool __fpu_restore_sig(void __us
        } else {
                if (__copy_from_user(&fpu->state.fxsave, buf_fx,
                                     sizeof(fpu->state.fxsave)))
 -                      return -EFAULT;
 +                      return false;
  
-               /* Reject invalid MXCSR values. */
-               if (fpu->state.fxsave.mxcsr & ~mxcsr_feature_mask)
-                       return false;
+               if (IS_ENABLED(CONFIG_X86_64)) {
+                       /* Reject invalid MXCSR values. */
+                       if (fpu->state.fxsave.mxcsr & ~mxcsr_feature_mask)
 -                              return -EINVAL;
++                              return false;
+               } else {
+                       /* Mask invalid bits out for historical reasons (broken hardware). */
+                       fpu->state.fxsave.mxcsr &= mxcsr_feature_mask;
+               }
  
                /* Enforce XFEATURE_MASK_FPSSE when XSAVE is enabled */
                if (use_xsave())
Simple merge
Simple merge