drm/xe/xe3: Add initial set of workarounds

Implement the initial set of workarounds for Xe3 IPs.

Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241008204626.55802-2-matthew.s.atwood@intel.com

diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
index 81b71903675e0d0907b9e83759eff31530f54f60..7c78496e6213cc48d0141a15f89c1a10b33c3da6 100644 (file)
--- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
@@ -186,6 +186,7 @@
 
 #define VDBOX_CGCTL3F10(base)                  XE_REG((base) + 0x3f10)
 #define   IECPUNIT_CLKGATE_DIS                 REG_BIT(22)
+#define   RAMDFTUNIT_CLKGATE_DIS               REG_BIT(9)
 
 #define VDBOX_CGCTL3F18(base)                  XE_REG((base) + 0x3f18)
 #define   ALNUNIT_CLKGATE_DIS                  REG_BIT(13)

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index f531eeeb89576d19f4a044737282ef71e4c387e4..42dc55cb23f4a3344b4944dfd90041b08bdf6b4c 100644 (file)
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -286,6 +286,9 @@
 #define   GAMTLBVEBOX0_CLKGATE_DIS             REG_BIT(16)
 #define   LTCDD_CLKGATE_DIS                    REG_BIT(10)
 
+#define UNSLCGCTL9454                          XE_REG(0x9454)
+#define   LSCFE_CLKGATE_DIS                    REG_BIT(4)
+
 #define XEHP_SLICE_UNIT_LEVEL_CLKGATE          XE_REG_MCR(0x94d4)
 #define   L3_CR2X_CLKGATE_DIS                  REG_BIT(17)
 #define   L3_CLKGATE_DIS                       REG_BIT(16)

diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index 94ea76b098ed6301c7780c38607f8e7982c88a23..0ee532eb26d600bc4be1894619a957fefd50f13a 100644 (file)
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -252,6 +252,34 @@ static const struct xe_rtp_entry_sr gt_was[] = {
          XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
        },
 
+       /* Xe3_LPG */
+
+       { XE_RTP_NAME("14021871409"),
+         XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0)),
+         XE_RTP_ACTIONS(SET(UNSLCGCTL9454, LSCFE_CLKGATE_DIS))
+       },
+
+       /* Xe3_LPM */
+
+       { XE_RTP_NAME("16021867713"),
+         XE_RTP_RULES(MEDIA_VERSION(3000),
+                      ENGINE_CLASS(VIDEO_DECODE)),
+         XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
+         XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
+       },
+       { XE_RTP_NAME("16021865536"),
+         XE_RTP_RULES(MEDIA_VERSION(3000),
+                      ENGINE_CLASS(VIDEO_DECODE)),
+         XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
+         XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
+       },
+       { XE_RTP_NAME("14021486841"),
+         XE_RTP_RULES(MEDIA_VERSION(3000), MEDIA_STEP(A0, B0),
+                      ENGINE_CLASS(VIDEO_DECODE)),
+         XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), RAMDFTUNIT_CLKGATE_DIS)),
+         XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
+       },
+
        {}
 };
 
@@ -568,6 +596,13 @@ static const struct xe_rtp_entry_sr engine_was[] = {
                             XE_RTP_ACTION_FLAG(ENGINE_BASE)))
        },
 
+       /* Xe3_LPG */
+
+       { XE_RTP_NAME("14021402888"),
+         XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), FUNC(xe_rtp_match_first_render_or_compute)),
+         XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
+       },
+
        {}
 };
 
@@ -739,6 +774,18 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
          XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX))
        },
 
+       /* Xe3_LPG */
+       { XE_RTP_NAME("14021490052"),
+         XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0),
+                      ENGINE_CLASS(RENDER)),
+         XE_RTP_ACTIONS(SET(FF_MODE,
+                            DIS_MESH_PARTIAL_AUTOSTRIP |
+                            DIS_MESH_AUTOSTRIP),
+                        SET(VFLSKPD,
+                            DIS_PARTIAL_AUTOSTRIP |
+                            DIS_AUTOSTRIP))
+       },
+
        {}
 };
 

diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
index 0154fbe154e9ad7c09fc7d66187cb48f0cc21409..264d6e116499ce9922cce5b126d4a3357fd88e59 100644 (file)
--- a/drivers/gpu/drm/xe/xe_wa_oob.rules
+++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
@@ -33,6 +33,7 @@
                GRAPHICS_VERSION(2004)
 22019338487    MEDIA_VERSION(2000)
                GRAPHICS_VERSION(2001)
+               MEDIA_VERSION(3000), MEDIA_STEP(A0, B0)
 22019338487_display    PLATFORM(LUNARLAKE)
 16023588340    GRAPHICS_VERSION(2001)
 14019789679    GRAPHICS_VERSION(1255)