x86/mm: Add 'mm' argument to unuse_temporary_mm()

In commit 209954cbc7d0 ("x86/mm/tlb: Update mm_cpumask lazily")
unuse_temporary_mm() grew the assumption that it gets used on
poking_mm exclusively. While this is currently true, lets not hard
code this assumption.

Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Rik van Riel <riel@surriel.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Link: https://lore.kernel.org/r/20250402094540.3586683-2-mingo@kernel.org

diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c
index f785d2335812497c949a974ba0ef78f0c2457ca7..95053e8a1378bb8e05f67721c9e9b8735db74f67 100644 (file)
--- a/arch/x86/kernel/alternative.c
+++ b/arch/x86/kernel/alternative.c
@@ -2161,14 +2161,14 @@ static inline struct mm_struct *use_temporary_mm(struct mm_struct *temp_mm)
 __ro_after_init struct mm_struct *text_poke_mm;
 __ro_after_init unsigned long text_poke_mm_addr;
 
-static inline void unuse_temporary_mm(struct mm_struct *prev_mm)
+static inline void unuse_temporary_mm(struct mm_struct *mm, struct mm_struct *prev_mm)
 {
        lockdep_assert_irqs_disabled();
 
        switch_mm_irqs_off(NULL, prev_mm, current);
 
        /* Clear the cpumask, to indicate no TLB flushing is needed anywhere */
-       cpumask_clear_cpu(raw_smp_processor_id(), mm_cpumask(text_poke_mm));
+       cpumask_clear_cpu(raw_smp_processor_id(), mm_cpumask(mm));
 
        /*
         * Restore the breakpoints if they were disabled before the temporary mm
@@ -2275,7 +2275,7 @@ static void *__text_poke(text_poke_f func, void *addr, const void *src, size_t l
         * instruction that already allows the core to see the updated version.
         * Xen-PV is assumed to serialize execution in a similar manner.
         */
-       unuse_temporary_mm(prev_mm);
+       unuse_temporary_mm(text_poke_mm, prev_mm);
 
        /*
         * Flushing the TLB might involve IPIs, which would require enabled