drm/amd/display: Fix for tile MST

- Set stream signal type to be SST when setting non-tile timing on MST
  tiled display.
  - Disable MST on sink after disabling MST link.
  - Enable MST on sink before enabling MST link.

Signed-off-by: Ding Wang <Ding.Wang@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index b878fb9697d7f92b08dfa33de4d3415199de0f2d..426f7f8187a62bf99dfdea500a3a2c0677542529 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1250,6 +1250,9 @@ static enum dc_status enable_link_dp_mst(struct pipe_ctx *pipe_ctx)
        if (link->public.cur_link_settings.lane_count != LANE_COUNT_UNKNOWN)
                return DC_OK;
 
+       /* set the sink to MST mode before enabling the link */
+       dp_enable_mst_on_sink(link, true);
+
        return enable_link_dp(pipe_ctx);
 }
 

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 9f12ba87827a01f553b6dbf062bd8013e7af494f..913b01cd7159ddef1855be5eb4c2090d0b3124f5 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2453,3 +2453,16 @@ bool dc_link_dp_set_test_pattern(
 
        return true;
 }
+
+void dp_enable_mst_on_sink(struct core_link *link, bool enable)
+{
+       unsigned char mstmCntl;
+
+       core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
+       if (enable)
+               mstmCntl |= DP_MST_EN;
+       else
+               mstmCntl &= (~DP_MST_EN);
+
+       core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
+}

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index 3b814592fd7093ca5983b54b126fcb3d588b844d..316df150c1d99193a0d0a71c67ffc24591dda3ee 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -129,6 +129,9 @@ void dp_disable_link_phy_mst(struct core_link *link, enum signal_type signal)
                return;
 
        dp_disable_link_phy(link, signal);
+
+       /* set the sink to SST mode after disabling the link */
+       dp_enable_mst_on_sink(link, false);
 }
 
 bool dp_set_hw_training_pattern(

diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
index b0cf8e00059c3f491395f1894aa9e50ee8ac839b..92c56e6f7588200b097312739186642f38808cb0 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
@@ -57,4 +57,6 @@ void detect_dp_sink_caps(struct core_link *link);
 
 bool is_dp_active_dongle(const struct core_link *link);
 
+void dp_enable_mst_on_sink(struct core_link *link, bool enable);
+
 #endif /* __DC_LINK_DP_H__ */