drm/i915: Extract i9xx_dpll_get_hw_state()

Start making the GMCH DPLL code a bit more like the more modern
platforms by separating out the DPLL hw state readout from the
rest of the pipe readout.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240412182703.19916-8-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a92b67adee9c1c59173a8749bffa5191bdb2d3c3..70ba8a9c671e3c40a1ddc46b6807498e88a30412 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3071,19 +3071,16 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
 
        i9xx_get_pfit_config(pipe_config);
 
+       i9xx_dpll_get_hw_state(crtc, &pipe_config->dpll_hw_state);
+
        if (DISPLAY_VER(dev_priv) >= 4) {
-               /* No way to read it out on pipes B and C */
-               if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
-                       tmp = dev_priv->display.state.chv_dpll_md[crtc->pipe];
-               else
-                       tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe));
+               tmp = pipe_config->dpll_hw_state.dpll_md;
                pipe_config->pixel_multiplier =
                        ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
                         >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
-               pipe_config->dpll_hw_state.dpll_md = tmp;
        } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
                   IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
-               tmp = intel_de_read(dev_priv, DPLL(crtc->pipe));
+               tmp = pipe_config->dpll_hw_state.dpll;
                pipe_config->pixel_multiplier =
                        ((tmp & SDVO_MULTIPLIER_MASK)
                         >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
@@ -3093,19 +3090,6 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
                 * function. */
                pipe_config->pixel_multiplier = 1;
        }
-       pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv,
-                                                       DPLL(crtc->pipe));
-       if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
-               pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv,
-                                                              FP0(crtc->pipe));
-               pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv,
-                                                              FP1(crtc->pipe));
-       } else {
-               /* Mask out read-only status bits. */
-               pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
-                                                    DPLL_PORTC_READY_MASK |
-                                                    DPLL_PORTB_READY_MASK);
-       }
 
        if (IS_CHERRYVIEW(dev_priv))
                chv_crtc_clock_get(crtc, pipe_config);

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index aa46e9e807868e64c476bc49cee2f027181c7f5f..693e22f06aeee6e4d1be18af957773c04ee063eb 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -385,6 +385,36 @@ static int i9xx_pll_refclk(struct drm_device *dev,
                return 48000;
 }
 
+void i9xx_dpll_get_hw_state(struct intel_crtc *crtc,
+                           struct intel_dpll_hw_state *hw_state)
+{
+       struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+
+       if (DISPLAY_VER(dev_priv) >= 4) {
+               u32 tmp;
+
+               /* No way to read it out on pipes B and C */
+               if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
+                       tmp = dev_priv->display.state.chv_dpll_md[crtc->pipe];
+               else
+                       tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe));
+
+               hw_state->dpll_md = tmp;
+       }
+
+       hw_state->dpll = intel_de_read(dev_priv, DPLL(crtc->pipe));
+
+       if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
+               hw_state->fp0 = intel_de_read(dev_priv, FP0(crtc->pipe));
+               hw_state->fp1 = intel_de_read(dev_priv, FP1(crtc->pipe));
+       } else {
+               /* Mask out read-only status bits. */
+               hw_state->dpll &= ~(DPLL_LOCK_VLV |
+                                   DPLL_PORTC_READY_MASK |
+                                   DPLL_PORTB_READY_MASK);
+       }
+}
+
 /* Returns the clock of the currently programmed mode of the given pipe. */
 void i9xx_crtc_clock_get(struct intel_crtc *crtc,
                         struct intel_crtc_state *pipe_config)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.h b/drivers/gpu/drm/i915/display/intel_dpll.h
index ac01bb19cc6c33f3c4290915eb05f39d1e763465..c11c182772667b3cdbb90d38c32ad191f84e0c91 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dpll.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll.h
@@ -13,6 +13,7 @@ struct drm_i915_private;
 struct intel_atomic_state;
 struct intel_crtc;
 struct intel_crtc_state;
+struct intel_dpll_hw_state;
 enum pipe;
 
 void intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv);
@@ -22,6 +23,8 @@ int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
                                    struct intel_crtc *crtc);
 int i9xx_calc_dpll_params(int refclk, struct dpll *clock);
 u32 i9xx_dpll_compute_fp(const struct dpll *dpll);
+void i9xx_dpll_get_hw_state(struct intel_crtc *crtc,
+                           struct intel_dpll_hw_state *hw_state);
 void vlv_compute_dpll(struct intel_crtc_state *crtc_state);
 void chv_compute_dpll(struct intel_crtc_state *crtc_state);