.intf = msm8998_intf,
        .vbif_count = ARRAY_SIZE(msm8998_vbif),
        .vbif = msm8998_vbif,
-       .reg_dma_count = 0,
        .perf = &msm8998_perf_data,
        .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
                     BIT(MDP_SSPP_TOP0_INTR2) | \
 
        .intf = sdm845_intf,
        .vbif_count = ARRAY_SIZE(sdm845_vbif),
        .vbif = sdm845_vbif,
-       .reg_dma_count = 1,
-       .dma_cfg = &sdm845_regdma,
        .perf = &sdm845_perf_data,
        .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
                     BIT(MDP_SSPP_TOP0_INTR2) | \
 
        .intf = sm8150_intf,
        .vbif_count = ARRAY_SIZE(sdm845_vbif),
        .vbif = sdm845_vbif,
-       .reg_dma_count = 1,
-       .dma_cfg = &sm8150_regdma,
        .perf = &sm8150_perf_data,
        .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
                     BIT(MDP_SSPP_TOP0_INTR2) | \
 
        .intf = sc8180x_intf,
        .vbif_count = ARRAY_SIZE(sdm845_vbif),
        .vbif = sdm845_vbif,
-       .reg_dma_count = 1,
-       .dma_cfg = &sm8150_regdma,
        .perf = &sc8180x_perf_data,
        .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
                     BIT(MDP_SSPP_TOP0_INTR2) | \
 
        .vbif = sdm845_vbif,
        .wb_count = ARRAY_SIZE(sm8250_wb),
        .wb = sm8250_wb,
-       .reg_dma_count = 1,
-       .dma_cfg = &sm8250_regdma,
        .perf = &sm8250_perf_data,
        .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
                     BIT(MDP_SSPP_TOP0_INTR2) | \
 
        .wb = sc7180_wb,
        .vbif_count = ARRAY_SIZE(sdm845_vbif),
        .vbif = sdm845_vbif,
-       .reg_dma_count = 1,
-       .dma_cfg = &sdm845_regdma,
        .perf = &sc7180_perf_data,
        .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
                     BIT(MDP_SSPP_TOP0_INTR2) | \
 
        .intf = sm8350_intf,
        .vbif_count = ARRAY_SIZE(sdm845_vbif),
        .vbif = sdm845_vbif,
-       .reg_dma_count = 1,
-       .dma_cfg = &sm8350_regdma,
        .perf = &sm8350_perf_data,
        .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
                     BIT(MDP_SSPP_TOP0_INTR2) | \
 
        .intf = sc8280xp_intf,
        .vbif_count = ARRAY_SIZE(sdm845_vbif),
        .vbif = sdm845_vbif,
-       .reg_dma_count = 1,
-       .dma_cfg = &sc8280xp_regdma,
        .perf = &sc8280xp_perf_data,
        .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
                     BIT(MDP_SSPP_TOP0_INTR2) | \
 
        .intf = sm8450_intf,
        .vbif_count = ARRAY_SIZE(sdm845_vbif),
        .vbif = sdm845_vbif,
-       .reg_dma_count = 1,
-       .dma_cfg = &sm8450_regdma,
        .perf = &sm8450_perf_data,
        .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
                     BIT(MDP_SSPP_TOP0_INTR2) | \
 
        .intf = sm8550_intf,
        .vbif_count = ARRAY_SIZE(sdm845_vbif),
        .vbif = sdm845_vbif,
-       .reg_dma_count = 1,
-       .dma_cfg = &sm8450_regdma,
        .perf = &sm8550_perf_data,
        .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
                     BIT(MDP_SSPP_TOP0_INTR2) | \
 
        },
 };
 
-static const struct dpu_reg_dma_cfg sc8280xp_regdma = {
-       .base = 0x0,
-       .version = 0x00020000,
-       .trigger_sel_off = 0x119c,
-       .xin_id = 7,
-       .clk_ctrl = DPU_CLK_CTRL_REG_DMA,
-};
-
-static const struct dpu_reg_dma_cfg sdm845_regdma = {
-       .base = 0x0, .version = 0x1, .trigger_sel_off = 0x119c
-};
-
-static const struct dpu_reg_dma_cfg sm8150_regdma = {
-       .base = 0x0, .version = 0x00010001, .trigger_sel_off = 0x119c
-};
-
-static const struct dpu_reg_dma_cfg sm8250_regdma = {
-       .base = 0x0,
-       .version = 0x00010002,
-       .trigger_sel_off = 0x119c,
-       .xin_id = 7,
-       .clk_ctrl = DPU_CLK_CTRL_REG_DMA,
-};
-
-static const struct dpu_reg_dma_cfg sm8350_regdma = {
-       .base = 0x400,
-       .version = 0x00020000,
-       .trigger_sel_off = 0x119c,
-       .xin_id = 7,
-       .clk_ctrl = DPU_CLK_CTRL_REG_DMA,
-};
-
-static const struct dpu_reg_dma_cfg sm8450_regdma = {
-       .base = 0x0,
-       .version = 0x00020000,
-       .trigger_sel_off = 0x119c,
-       .xin_id = 7,
-       .clk_ctrl = DPU_CLK_CTRL_REG_DMA,
-};
-
 /*************************************************************
  * PERF data config
  *************************************************************/
 
        u32 memtype_count;
        u32 memtype[MAX_XIN_COUNT];
 };
-/**
- * struct dpu_reg_dma_cfg - information of lut dma blocks
- * @id                 enum identifying this block
- * @base               register offset of this block
- * @features           bit mask identifying sub-blocks/features
- * @version            version of lutdma hw block
- * @trigger_sel_off    offset to trigger select registers of lutdma
- */
-struct dpu_reg_dma_cfg {
-       DPU_HW_BLK_INFO;
-       u32 version;
-       u32 trigger_sel_off;
-       u32 xin_id;
-       enum dpu_clk_ctrl_type clk_ctrl;
-};
 
 /**
  * Define CDP use cases
        u32 wb_count;
        const struct dpu_wb_cfg *wb;
 
-       u32 reg_dma_count;
-       const struct dpu_reg_dma_cfg *dma_cfg;
-
        u32 ad_count;
 
        u32 dspp_count;