ARM: tegra: paz00: fix wrong UART port on mini-pcie plug

UARTC is connected to the mini-pcie port.

Signed-off-by: Marc Dietrich <marvin24@gmx.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>

diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts
index a94e92c98829635eccde60e50b50e2e6ba3d1243..825d2957da0b819a8ac9204df02dff60fee9dbbc 100644 (file)
--- a/arch/arm/boot/dts/tegra-paz00.dts
+++ b/arch/arm/boot/dts/tegra-paz00.dts
@@ -46,11 +46,11 @@
        };
 
        serial@70006200 {
-               status = "disable";
+               clock-frequency = <216000000>;
        };
 
        serial@70006300 {
-               clock-frequency = <216000000>;
+               status = "disable";
        };
 
        serial@70006400 {

diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c
index fcf4f377b1dcf0e99d11fdf62f228a1f05b1dda1..330afdfa24754ae773238f45f855db0407c7dd57 100644 (file)
--- a/arch/arm/mach-tegra/board-paz00.c
+++ b/arch/arm/mach-tegra/board-paz00.c
@@ -60,9 +60,9 @@ static struct plat_serial8250_port debug_uart_platform_data[] = {
                .uartclk        = 216000000,
        }, {
                /* serial port on mini-pcie */
-               .membase        = IO_ADDRESS(TEGRA_UARTD_BASE),
-               .mapbase        = TEGRA_UARTD_BASE,
-               .irq            = INT_UARTD,
+               .membase        = IO_ADDRESS(TEGRA_UARTC_BASE),
+               .mapbase        = TEGRA_UARTC_BASE,
+               .irq            = INT_UARTC,
                .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
                .type           = PORT_TEGRA,
                .iotype         = UPIO_MEM,
@@ -174,7 +174,7 @@ static void __init tegra_paz00_fixup(struct tag *tags, char **cmdline,
 static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = {
        /* name         parent          rate            enabled */
        { "uarta",      "pll_p",        216000000,      true },
-       { "uartd",      "pll_p",        216000000,      true },
+       { "uartc",      "pll_p",        216000000,      true },
 
        { "pll_p_out4", "pll_p",        24000000,       true },
        { "usbd",       "clk_m",        12000000,       false },