#include <dt-bindings/clock/r8a7794-clock.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/power/r8a7794-sysc.h>
 
 / {
        compatible = "renesas,r8a7794";
                        compatible = "arm,cortex-a7";
                        reg = <0>;
                        clock-frequency = <1000000000>;
+                       power-domains = <&sysc R8A7794_PD_CA7_CPU0>;
                        next-level-cache = <&L2_CA7>;
                };
 
                        compatible = "arm,cortex-a7";
                        reg = <1>;
                        clock-frequency = <1000000000>;
+                       power-domains = <&sysc R8A7794_PD_CA7_CPU1>;
                        next-level-cache = <&L2_CA7>;
                };
        };
 
        L2_CA7: cache-controller@1 {
                compatible = "cache";
+               power-domains = <&sysc R8A7794_PD_CA7_SCU>;
                cache-unified;
                cache-level = <2>;
        };
                };
        };
 
+       sysc: system-controller@e6180000 {
+               compatible = "renesas,r8a7794-sysc";
+               reg = <0 0xe6180000 0 0x0200>;
+               #power-domain-cells = <1>;
+       };
+
        ipmmu_sy0: mmu@e6280000 {
                compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
                reg = <0 0xe6280000 0 0x1000>;