#undef GEN6_WRITE_FOOTER
 #undef GEN6_WRITE_HEADER
 
-#define ASSIGN_WRITE_MMIO_VFUNCS(x) \
+#define ASSIGN_WRITE_MMIO_VFUNCS(i915, x) \
 do { \
-       dev_priv->uncore.funcs.mmio_writeb = x##_write8; \
-       dev_priv->uncore.funcs.mmio_writew = x##_write16; \
-       dev_priv->uncore.funcs.mmio_writel = x##_write32; \
+       (i915)->uncore.funcs.mmio_writeb = x##_write8; \
+       (i915)->uncore.funcs.mmio_writew = x##_write16; \
+       (i915)->uncore.funcs.mmio_writel = x##_write32; \
 } while (0)
 
-#define ASSIGN_READ_MMIO_VFUNCS(x) \
+#define ASSIGN_READ_MMIO_VFUNCS(i915, x) \
 do { \
-       dev_priv->uncore.funcs.mmio_readb = x##_read8; \
-       dev_priv->uncore.funcs.mmio_readw = x##_read16; \
-       dev_priv->uncore.funcs.mmio_readl = x##_read32; \
-       dev_priv->uncore.funcs.mmio_readq = x##_read64; \
+       (i915)->uncore.funcs.mmio_readb = x##_read8; \
+       (i915)->uncore.funcs.mmio_readw = x##_read16; \
+       (i915)->uncore.funcs.mmio_readl = x##_read32; \
+       (i915)->uncore.funcs.mmio_readq = x##_read64; \
 } while (0)
 
 
                i915_pmic_bus_access_notifier;
 
        if (IS_GEN(dev_priv, 2, 4) || intel_vgpu_active(dev_priv)) {
-               ASSIGN_WRITE_MMIO_VFUNCS(gen2);
-               ASSIGN_READ_MMIO_VFUNCS(gen2);
+               ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen2);
+               ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen2);
        } else if (IS_GEN5(dev_priv)) {
-               ASSIGN_WRITE_MMIO_VFUNCS(gen5);
-               ASSIGN_READ_MMIO_VFUNCS(gen5);
+               ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen5);
+               ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen5);
        } else if (IS_GEN(dev_priv, 6, 7)) {
-               ASSIGN_WRITE_MMIO_VFUNCS(gen6);
+               ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen6);
 
                if (IS_VALLEYVIEW(dev_priv)) {
                        ASSIGN_FW_DOMAINS_TABLE(__vlv_fw_ranges);
-                       ASSIGN_READ_MMIO_VFUNCS(fwtable);
+                       ASSIGN_READ_MMIO_VFUNCS(dev_priv, fwtable);
                } else {
-                       ASSIGN_READ_MMIO_VFUNCS(gen6);
+                       ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen6);
                }
        } else if (IS_GEN8(dev_priv)) {
                if (IS_CHERRYVIEW(dev_priv)) {
                        ASSIGN_FW_DOMAINS_TABLE(__chv_fw_ranges);
-                       ASSIGN_WRITE_MMIO_VFUNCS(fwtable);
-                       ASSIGN_READ_MMIO_VFUNCS(fwtable);
+                       ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, fwtable);
+                       ASSIGN_READ_MMIO_VFUNCS(dev_priv, fwtable);
 
                } else {
-                       ASSIGN_WRITE_MMIO_VFUNCS(gen8);
-                       ASSIGN_READ_MMIO_VFUNCS(gen6);
+                       ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen8);
+                       ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen6);
                }
        } else {
                ASSIGN_FW_DOMAINS_TABLE(__gen9_fw_ranges);
-               ASSIGN_WRITE_MMIO_VFUNCS(fwtable);
-               ASSIGN_READ_MMIO_VFUNCS(fwtable);
+               ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, fwtable);
+               ASSIGN_READ_MMIO_VFUNCS(dev_priv, fwtable);
                if (HAS_DECOUPLED_MMIO(dev_priv)) {
                        dev_priv->uncore.funcs.mmio_readl =
                                                gen9_decoupled_read32;
 
        i915_check_and_clear_faults(dev_priv);
 }
-#undef ASSIGN_WRITE_MMIO_VFUNCS
-#undef ASSIGN_READ_MMIO_VFUNCS
 
 void intel_uncore_fini(struct drm_i915_private *dev_priv)
 {
 }
 
 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftests/mock_uncore.c"
 #include "selftests/intel_uncore.c"
 #endif
 
 #include "mock_gem_device.h"
 #include "mock_gem_object.h"
 #include "mock_gtt.h"
+#include "mock_uncore.h"
 
 void mock_device_flush(struct drm_i915_private *i915)
 {
        mkwrite_device_info(i915)->gen = -1;
 
        spin_lock_init(&i915->mm.object_stat_lock);
+       mock_uncore_init(i915);
 
        init_waitqueue_head(&i915->gpu_error.wait_queue);
        init_waitqueue_head(&i915->gpu_error.reset_queue);
 
--- /dev/null
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "mock_uncore.h"
+
+#define __nop_write(x) \
+static void \
+nop_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { }
+__nop_write(8)
+__nop_write(16)
+__nop_write(32)
+
+#define __nop_read(x) \
+static u##x \
+nop_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { return 0; }
+__nop_read(8)
+__nop_read(16)
+__nop_read(32)
+__nop_read(64)
+
+void mock_uncore_init(struct drm_i915_private *i915)
+{
+       ASSIGN_WRITE_MMIO_VFUNCS(i915, nop);
+       ASSIGN_READ_MMIO_VFUNCS(i915, nop);
+}
 
--- /dev/null
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __MOCK_UNCORE_H
+#define __MOCK_UNCORE_H
+
+void mock_uncore_init(struct drm_i915_private *i915);
+
+#endif /* !__MOCK_UNCORE_H */