drm/amdgpu/gfx11: fallback to driver reset compute queue directly (v2)

Since the MES FW resets kernel compute queue always failed, this
may caused by the KIQ failed to process unmap KCQ. So, before MES
FW work properly that will fallback to driver executes dequeue and
resets SPI directly. Besides, rework the ring reset function and make
the busy ring type reset in each function respectively.

Acked-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 986cd5a3d56068e70a8d302d9419a48fe64efda9..b923b70b2abd5fa9163e05bca2002ccd27a60e19 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -3984,13 +3984,13 @@ static int gfx_v11_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
        return 0;
 }
 
-static int gfx_v11_0_gfx_init_queue(struct amdgpu_ring *ring)
+static int gfx_v11_0_gfx_init_queue(struct amdgpu_ring *ring, bool reset)
 {
        struct amdgpu_device *adev = ring->adev;
        struct v11_gfx_mqd *mqd = ring->mqd_ptr;
        int mqd_idx = ring - &adev->gfx.gfx_ring[0];
 
-       if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
+       if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) {
                memset((void *)mqd, 0, sizeof(*mqd));
                mutex_lock(&adev->srbm_mutex);
                soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
@@ -4026,7 +4026,7 @@ static int gfx_v11_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
 
                r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
                if (!r) {
-                       r = gfx_v11_0_gfx_init_queue(ring);
+                       r = gfx_v11_0_gfx_init_queue(ring, false);
                        amdgpu_bo_kunmap(ring->mqd_obj);
                        ring->mqd_ptr = NULL;
                }
@@ -4321,13 +4321,13 @@ static int gfx_v11_0_kiq_init_queue(struct amdgpu_ring *ring)
        return 0;
 }
 
-static int gfx_v11_0_kcq_init_queue(struct amdgpu_ring *ring)
+static int gfx_v11_0_kcq_init_queue(struct amdgpu_ring *ring, bool reset)
 {
        struct amdgpu_device *adev = ring->adev;
        struct v11_compute_mqd *mqd = ring->mqd_ptr;
        int mqd_idx = ring - &adev->gfx.compute_ring[0];
 
-       if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
+       if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) {
                memset((void *)mqd, 0, sizeof(*mqd));
                mutex_lock(&adev->srbm_mutex);
                soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
@@ -4391,7 +4391,7 @@ static int gfx_v11_0_kcq_resume(struct amdgpu_device *adev)
                        goto done;
                r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
                if (!r) {
-                       r = gfx_v11_0_kcq_init_queue(ring);
+                       r = gfx_v11_0_kcq_init_queue(ring, false);
                        amdgpu_bo_kunmap(ring->mqd_obj);
                        ring->mqd_ptr = NULL;
                }
@@ -6544,18 +6544,76 @@ static void gfx_v11_0_emit_mem_sync(struct amdgpu_ring *ring)
        amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
 }
 
-static int gfx_v11_0_reset_ring(struct amdgpu_ring *ring, unsigned int vmid)
+static int gfx_v11_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid)
 {
+       struct amdgpu_device *adev = ring->adev;
        int r;
 
        r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid);
        if (r)
                return r;
 
-       /* reset the ring */
-       ring->wptr = 0;
-       *ring->wptr_cpu_addr = 0;
-       amdgpu_ring_clear_ring(ring);
+       r = amdgpu_bo_reserve(ring->mqd_obj, false);
+       if (unlikely(r != 0)) {
+               dev_err(adev->dev, "fail to resv mqd_obj\n");
+               return r;
+       }
+       r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
+       if (!r) {
+               r = gfx_v11_0_gfx_init_queue(ring, true);
+               amdgpu_bo_kunmap(ring->mqd_obj);
+               ring->mqd_ptr = NULL;
+       }
+       amdgpu_bo_unreserve(ring->mqd_obj);
+       if (r) {
+               dev_err(adev->dev, "fail to unresv mqd_obj\n");
+               return r;
+       }
+
+       r = amdgpu_mes_map_legacy_queue(adev, ring);
+       if (r) {
+               dev_err(adev->dev, "failed to remap kgq\n");
+               return r;
+       }
+
+       return amdgpu_ring_test_ring(ring);
+}
+
+static int gfx_v11_0_reset_kcq(struct amdgpu_ring *ring, unsigned int vmid)
+{
+       struct amdgpu_device *adev = ring->adev;
+       int r;
+
+       gfx_v11_0_set_safe_mode(adev, 0);
+       mutex_lock(&adev->srbm_mutex);
+       soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
+       WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2);
+       WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1);
+       soc21_grbm_select(adev, 0, 0, 0, 0);
+       mutex_unlock(&adev->srbm_mutex);
+       gfx_v11_0_unset_safe_mode(adev, 0);
+
+       r = amdgpu_bo_reserve(ring->mqd_obj, false);
+       if (unlikely(r != 0)) {
+               dev_err(adev->dev, "fail to resv mqd_obj\n");
+               return r;
+       }
+       r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
+       if (!r) {
+               r = gfx_v11_0_kcq_init_queue(ring, true);
+               amdgpu_bo_kunmap(ring->mqd_obj);
+               ring->mqd_ptr = NULL;
+       }
+       amdgpu_bo_unreserve(ring->mqd_obj);
+       if (r) {
+               dev_err(adev->dev, "fail to unresv mqd_obj\n");
+               return r;
+       }
+       r = amdgpu_mes_map_legacy_queue(adev, ring);
+       if (r) {
+               dev_err(adev->dev, "failed to remap kcq\n");
+               return r;
+       }
 
        return amdgpu_ring_test_ring(ring);
 }
@@ -6761,7 +6819,7 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = {
        .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait,
        .soft_recovery = gfx_v11_0_ring_soft_recovery,
        .emit_mem_sync = gfx_v11_0_emit_mem_sync,
-       .reset = gfx_v11_0_reset_ring,
+       .reset = gfx_v11_0_reset_kgq,
 };
 
 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = {
@@ -6799,7 +6857,7 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = {
        .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait,
        .soft_recovery = gfx_v11_0_ring_soft_recovery,
        .emit_mem_sync = gfx_v11_0_emit_mem_sync,
-       .reset = gfx_v11_0_reset_ring,
+       .reset = gfx_v11_0_reset_kcq,
 };
 
 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_kiq = {